July 2023

Webinar on Demand

Missed this webinar? Watch the video recording and download the UCIe PHY model in SystemVerilog.

This application note showcases three different ways of modeling a charge-pump voltage generator circuit.

With the new '--real' option of MODELZEN, it is handy to create SystemVerilog models of which top-level I/O ports are all real types.

With this primitive, you can model a nonlinear DC transfer function of a circuit which varies with a set of digital input values.

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More

Webinar on Silicon Photonics Modeling & Simulation, Modeling Nonlinear PAM4 Transmitters, and More

XMODEL at DAC 2024, Modeling an Adaptive DFE Receiver, and More

Modeling a Phase Interpolator with INL/DNL, Using PSL Assertions for Analog Checks, and More

Modeling an Oscillator with Resettable Phase, Multiple Outputs, and Arbitrary Waveforms