Technical Paper
UVM testbench for verifying the global convergence of DFE adaptation loop
This UVM testbench checks whether a DFE adaptation loop always settles to the same final state regardless of the initial state.
October 2024
Tip of the Month
Measuring the open-loop transfer function and phase margin of a PLL
You can measure the open-loop transfer function of a PLL without breaking its feedback loop using a simplified Middlebrook method.
Primitive of the Month
probe_ac
With this primitive, you can measure the frequency-domain transfer function of your circuit/model while running a time-domain simulation in SystemVerilog.
Latest Issues
May 2026
Estimating Eye Openings and FFE/DFE Settings from Channel SBR
April 2026
Delay, Delay, Delay!
March 2026
EQCHECK, Adaptive Decision-Feedback Equalizer, and More
February 2026
XMODEL at DVCon US, Introducing EQCHECK, and More
January 2026
Generating Random Step Sequences for Stress-Testing, Measuring Single-Bit Responses, and More