Learn UCIe by seeing it in action! This webinar demonstrates the modeling and simulation of the electrical and logical layers of the Universal Chip Interconnect Express (UCIe) PHY in SystemVerilog.
This application note illustrates the process of developing Volterra-series models for nonlinear circuits with XMODEL.
Learn how you can constrain the value space of the UDM's mode bits and make its characterization faster.
With this primitive, you can compute a polynomial function of xreal-type signals.
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More
UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More