July 2023

Webinar on Demand

Missed this webinar? Watch the video recording and download the UCIe PHY model in SystemVerilog.

This application note showcases three different ways of modeling a charge-pump voltage generator circuit.

With the new '--real' option of MODELZEN, it is handy to create SystemVerilog models of which top-level I/O ports are all real types.

With this primitive, you can model a nonlinear DC transfer function of a circuit which varies with a set of digital input values.

Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More

Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More

UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More