February 2024

Upcoming Event

Scientific Analog is coming to San Jose, CA! Get up to speed with the latest techniques for verifying analog circuits in SystemVerilog & UVM.

This application note shows how to model the low-power (LP) and high-speed (HS) transceivers of MIPI D-PHY.

When measuring the frequency of a clock input, why does 'meas_freq' primitive produce twice its frequency value?

This primitive outputs the frequency of the input clock.

Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More

Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More

UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More