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Mar 5, 11:00am / Poster Session

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A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator by Charles Dančak

A standard UVM testbench is developed to apply benchtop-style directed tests to an on-chip low-dropout CMOS voltage regulator. Eight directed tests verify the regulator’s DC and AC response to line and load fluctuations, its programmed operating modes, etc. To enhance the effectiveness of the low-level directed tests in reaching unexpected corner cases, we employ high-level UVM randomization techniques to generate a randsequence of transient tests. The sub-cycle timing aspects of stimulus and response for transient testing are handled using the global uvm_event_pool. Our goal is to present the UVM testbench mechanisms and coding techniques that proved most effective for an area of analog/ mixed-signal testing which lies outside the usual scope of chip-level UVM testbench development.