Upcoming Event
Meet Scientific Analog at DVCon U.S. 2022
Meet our experts on verifying analog circuits in SystemVerilog/UVM!
February 2022
New Tutorial
MODELZEN Online Interactive Demo
Seeing is believing! Witness how easy it is to auto-extract models from circuits using MODELZEN.
Primitive of the Month
pulse_gen
This primitive can produce digital pulses with periodic or arbitrary waveforms.
Tip of the Month
Generating a digital pulse alternating between long and short pulsewidths
Learn how to utilize the new feature of 'pulse_gen' primitive to generate digital pulses with irregular waveforms.
Latest Issues
November 2025
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More
October 2025
A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More
September 2025
XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More
August 2025
Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More
July 2025
Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More