This webinar focuses on how to write a SystemVerilog OOP testbench to verify an analog/mixed-signal circuit controlled by digital logic. No language extensions like Verilog-AMS are used. The key testbench components are presented in a step-by-step manner, such as the test sequence, driver, monitor, and scoreboard. A few advanced OOP techniques, like randomizing a real-valued sine frequency, are introduced as well.

Using a digitally-programmable audio bandpass filter with power-down/bypass modes as an example, methods of reaching 100% functional coverage of both the digital modes and analog frequencies are examined. The testbench performs both the random and directed tests, and the analog assertions check the leakage current and bias voltage levels during the bypass and recovery mode, respectively. The scoreboard data reports voltage gains within 2% of SPICE over the filter’s entire passband.