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XMODEL lets you simulate analog models in SystemVerilog. The analog models can be composed in a top-down fashion using GLISTER or extracted in a bottom-up fashion using MODELZEN. Sounds like fun? Find out more at DVCon U.S. 2024!

Paper: A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator by Charles Dančak (Mar 5, 11:00am / Poster Session)

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