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XMODEL offers the best way to verify analog/mixed-signal circuits in SystemVerilog without compromising speed or accuracy. Create SystemVerilog models of your analog circuits in a top-down fashion using GLISTER or in a bottom-up fashion using MODELZEN, and simulate them efficiently and thoroughly along with digital models using a UVM testbench!

Paper: UVM Testbench for Adaptive Equalizer

October 16, 2:15 PM | Forum 5 | Session 3B

A digital adaptation controller for a wireline decision feedback equalizer may converge to different final states depending on its initial states. This paper demonstrates a UVM testbench that aims to verify the global convergence property of such an analog/mixed-signal system.