DVCon Europe 2024

Meet Us

October 15-16 / Booth# 17

Meet our experts and learn why XMODEL is the best way to verify analog circuits in SystemVerilog.

Paper: UVM Testbench for Adaptive Equalizer

October 16, 2:15 PM | Forum 5 | Session 3B

A digital adaptation controller for a wireline decision feedback equalizer may converge to different final states depending on its initial states. This paper demonstrates a UVM testbench that aims to verify the global convergence property of such an analog/mixed-signal system.

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XMODEL

XMODEL

The fastest way to run analog simulation in SystemVerilog

GLISTER

GLISTER

Build top-down analog models in schematic forms

MODELZEN

MODELZEN

Auto-extract bottom-up analog models from your circuits

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