October 15-16 / Booth# 17
Meet our experts and learn why XMODEL is the best way to verify analog circuits in SystemVerilog.
October 16, 2:15 PM | Forum 5 | Session 3B
A digital adaptation controller for a wireline decision feedback equalizer may converge to different final states depending on its initial states. This paper demonstrates a UVM testbench that aims to verify the global convergence property of such an analog/mixed-signal system.