Technical Paper
UVM testbench for verifying the global convergence of DFE adaptation loop
This UVM testbench checks whether a DFE adaptation loop always settles to the same final state regardless of the initial state.
October 2024
Tip of the Month
Measuring the open-loop transfer function and phase margin of a PLL
You can measure the open-loop transfer function of a PLL without breaking its feedback loop using a simplified Middlebrook method.
Primitive of the Month
probe_ac
With this primitive, you can measure the frequency-domain transfer function of your circuit/model while running a time-domain simulation in SystemVerilog.
Latest Issues
November 2025
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More
October 2025
A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More
September 2025
XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More
August 2025
Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More
July 2025
Analyzing the Power-Saving Benefits of DBI Encoding for High-Speed Transceivers and More