Technical Paper
UVM testbench for verifying the global convergence of DFE adaptation loop
This UVM testbench checks whether a DFE adaptation loop always settles to the same final state regardless of the initial state.
October 2024
Tip of the Month
Measuring the open-loop transfer function and phase margin of a PLL
You can measure the open-loop transfer function of a PLL without breaking its feedback loop using a simplified Middlebrook method.
Primitive of the Month
probe_ac
With this primitive, you can measure the frequency-domain transfer function of your circuit/model while running a time-domain simulation in SystemVerilog.
Latest Issues
December 2024
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
November 2024
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More
October 2024
UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More
September 2024
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
August 2024
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More