November 2020

ARTICLE OF THE MONTH

SystemVerilog OOP Testbench for Analog Filter: A Tutorial (Part 1)

Read this article and learn how to build an OOP-style testbench for analog circuits! Its hands-on example offers basic OOP concepts, testbench guidelines, and practical coding insights.

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PRIMITIVE OF THE MONTH

meas_pp

This primitive measures the peak-to-peak value of a signal within a time interval.

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TIP OF THE MONTH

Mapping UDMs in the technology configuration file

Here is how if you want to define UDM mapping within the technology configuration file.

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MODEL OF THE MONTH

Slew-rate controlled driver

Check out how to model a driver circuit with variable rise/fall times.

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Latest Issues

December 2024

Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More

November 2024

Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More

October 2024

UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More

September 2024

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

August 2024

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More