This second part of the article describes how to write an OOP-style SystemVerilog testbench that generates randomized test sequences, check analog assertions, and report coverages for an analog circuit with multiple operating modes.
New to XMODEL? Get up to speed by watching this latest video introducing XMODEL, GLISTER, and MODELZEN.
Learn how to model the PSIJ effects in a clock distribution network with a 'delay_to_clk' primitive and measure its frequency characteristics using a 'probe_ac' primitive.
This release adds many improvements and bug fixes including the MODELZEN support for unpacked arrays of 'xbit' and 'xreal' signals and a property for grouping auxiliary instances with the main instance.
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More
UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More