June 2022

Upcoming Event

Meet our experts in person and learn why XMODEL is the best way to verify analog circuits in SystemVerilog!

This application note models the duty-cycle corrector presented by James S. Humble, et al., in their 2006 ISSCC paper.

Check out how to dump the time instants of the clock's transition edges into a text file for post-processing.

This primitive measures the time of each input event being triggered.

This release improves the XMODEL's stability of circuit-level simulation and the MODELZEN support for CDL-format netlists.

Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More

Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More

UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More