July 2021

Model of the Month

DLL with a replica loop

Check out this model for a delay-locked loop (DLL) that operates over a wide frequency range without false locks using a replica loop, published by Y. Moon, et al. in 2000.

Tip of the Month

Extracting multi-port transmission line models from S-parameter files

With the new 'sparam_to_tline' utility, you can now extract a multi-port transmission line model including all the port-to-port transfer functions such as reflections and crosstalks from an S-parameter file.

Primitive of the Month

dff_xbit

This primitive models a D-flipflop, with optional setup and hold time violation checks.

XMODEL Release Updates

2021.07 Release

This release adds the support for UDM mappings on individual slices of parallel instances, and internal current probing for variable RLC and switch primitives.

Latest Issues

December 2024

Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More

November 2024

Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More

October 2024

UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More

September 2024

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

August 2024

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More