Model of the Month
DLL with a replica loop
Check out this model for a delay-locked loop (DLL) that operates over a wide frequency range without false locks using a replica loop, published by Y. Moon, et al. in 2000.
Check out this model for a delay-locked loop (DLL) that operates over a wide frequency range without false locks using a replica loop, published by Y. Moon, et al. in 2000.
With the new 'sparam_to_tline'
utility, you can now extract a multi-port transmission line model including all the port-to-port transfer functions such as reflections and crosstalks from an S-parameter file.
This primitive models a D-flipflop, with optional setup and hold time violation checks.
This release adds the support for UDM mappings on individual slices of parallel instances, and internal current probing for variable RLC and switch primitives.
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More
UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More