Upcoming Tutorial
Harnessing the Power of UVM for AMS Verification with XMODEL
Don't miss the opportunity to join this 3-hour hands-on tutorial at DVCon US 2023 and learn how to write UVM testbenches for analog/mixed-signal circuits!
January 2023
Tip of the Month
Scaling the Bandwidth of a Given Channel Model
Want to simulate your high-speed transceiver model while gradually varying the frequency-dependent loss of the channel? Here is a simple tip on how.
Model of the Month
Modeling a Track-and-Hold Circuit
Check out these two simple ways of modeling a track-and-hold circuit.
Primitive of the Month
sample
This primitive models a sample-and-hold circuit, sampling the input at the clock's triggering edge and holding it til the next edge.
Latest Issues
December 2025
Season's Greetings, Checking a Clocked Comparator's Correct Output, and More
November 2025
Checking the Settling of an Analog Signal, Handling Inherited Nets with Legacy SPICE Netlisters, and More
October 2025
A UVM Testbench for Worst-Case Analysis Using Bayesian Optimization and More
September 2025
XMODEL at DVCon Europe, Evaluating Transceivers with Multi-Drop Channels, and More
August 2025
Modeling Variations in ReRAMs, Supporting RNM Nettypes, and More