Primitive of the Month
probe_dc
This primitive lets you measure the DC transfer function of your circuit model in a single simulation run.
January 2021
Tip of the Month
Simulating the DC transfer characteristics of a circuit model
Learn how to perform DC analysis on your model and plot its DC transfer function using the new 'probe_dc' primitive and 'meas_dc' script.
Model of the Month
Successive approximation register (SAR) ADC
Check out how to model a SAR ADC made of a charge-redistribution DAC and successive approximation FSM.
XMODEL Release Updates
2021.01 Release
This release introduces 'probe_dc' primitive, adds multiprocessing support for UDMs, and generates parameterized symbol views for Verilog modules with variable port widths.
Latest Issues
December 2024
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
November 2024
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More
October 2024
UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More
September 2024
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
August 2024
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More