Upcoming Event
Meet Scientific Analog at DVCon U.S. 2023
Scientific Analog is coming to San Jose, CA! Grab this opportunity to meet our experts on verifying analog circuits in SystemVerilog & UVM.
February 2023
Tip of the Month
Displaying the progress of XMODEL simulation
Wondering how far the simulation has run? You can enable a progress display just with a mouse click.
Model of the Month
Modeling the pulling behavior of an injection-locked oscillator (ILO)
This simple example demonstrates the pulling behavior of an ILO where the phase and frequency of the ILO exhibit beat notes instead of locking at constant values.
Primitive of the Month
ilo
This primitive models an injection-locked oscillator with multiple injection inputs and multiple phase outputs.
Latest Issues
December 2024
Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More
November 2024
Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More
October 2024
UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More
September 2024
XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More
August 2024
Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More