February 2022

Upcoming Event

Meet our experts on verifying analog circuits in SystemVerilog/UVM!

Seeing is believing! Witness how easy it is to auto-extract models from circuits using MODELZEN.

This primitive can produce digital pulses with periodic or arbitrary waveforms.

Learn how to utilize the new feature of 'pulse_gen' primitive to generate digital pulses with irregular waveforms.

Modeling Mixed-Signal Processing-in-Memory Circuits, Filtering Phase Noise, and More

Modeling a Digital LDO, Tips on Modeling High-Pass Filters, and More

UVM Testbench for Verifying Adaptive DFE, Measuring the PLL's Open-Loop Transfer Function, and More

XMODEL at DVCon Europe 2024, Modeling SRAM Array, and More

Modeling PCIe Receiver Detection Circuit, Exporting XWAVE Analysis Results, and More