DVCon Europe 2024
Jaeha Kim, “A UVM Testbench for Checking the Global Convergence of Analog/Mixed-Signal Systems: An Adaptive Decision-Feedback Equalizer Example”, Design and Verification Conference and Exhibition (DVCon) Europe, 2024.
A UVM testbench capable of verifying the global convergence property of an analog/mixed-signal system is presented. For example, a sign-sign LMS adaptation algorithm for a decision-feedback equalizer (DFE) may converge to a false final state depending on the initial state. To detect the existence of such false final states, the testbench launches a sequence of trial runs, each starting from a random, unvisited initial state, until all possible states of the system are tried or traversed, or a problematic initial state is found. The simulation is run entirely in SystemVerilog by modeling the analog components of the high-speed wireline transceiver using the XMODEL primitives. To generate a sequence of trial runs based on the previous results and evaluate the termination conditions, the testbench utilizes a shared state coverage database and a global UVM event. The experimental results show that the testbench swiftly uncovers the false final states caused by high channel loss or insufficient constraints, and successfully confirms the global convergence of the adaptation loop when no such issues exist.
DVCon U.S. 2024
Charles Dancak, “A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator”, Design and Verification Conference and Exhibition (DVCon) US, 2024.
A UVM-compliant testbench is developed to apply benchtop-style directed tests to an on-chip low-dropout CMOS voltage regulator. Eight directed tests verify the regulator’s DC and AC response to line and load fluctuations, its programmed operating modes, power-supply rejection, etc. To enhance the effectiveness of the low-level directed tests in reaching unexpected corner cases, we apply high-level UVM randomization techniques to generate a randsequence of transient tests. Sub-cycle timing for stimulus and response is managed by means of the uvm_event_pool. Our goal is to present the UVM testbench mechanisms and coding techniques that proved most effective in verifying the circuit-level functionality of analog/mixed-signal blocks—a topic outside the usual scope of chip-level UVM testbench development.
DVCon U.S. 2023
Jaeha Kim, “A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers”, Design and Verification Conference and Exhibition (DVCon) US, 2023.
This paper demonstrates a UVM testbench that can measure the jitter tolerance (JTOL) characteristics of a high-speed wireline receiver. This JTOL measurement requires an iterative search finding the maximum magnitude of the sinusoidal jitter (SJ) that keeps the bit-error rate (BER) of the receiver below the target rate (e.g., 10-12). The presented UVM testbench adopts the reactive stimulus technique to perform the search for an analog/mixed-signal system, i.e., checking its BERs while varying the SJ frequencies and magnitudes. The UVM testbench also encapsulates all the analog/mixed-signal contents within the fixture module so that the rest of the testbench can be built using the standard UVM components. The model of the high-speed transceiver and the fixture instrumentations to apply stimuli and measure responses are composed with XMODEL primitives, which enable event-driven simulation of analog/mixed-signal circuits in SystemVerilog. A case with an example 16-Gb/s high-speed wireline receiver model shows that the presented testbench can measure the JTOL characteristics for 20 frequency points after performing 106 BER tests for a total duration of 41 minutes.