ADC_SuccApproxADC : A successive approximation register analog-to-digital converter (ADC)
A successive approximation register analog-to-digital converter (SAR-ADC) digitizes an analog input in
into a digital output out
using a binary search algorithm (i.e. successive approximation algorithm).
This SAR-ADC model is composed of an analog front-end, a comparator, and a digital finite-state machine. The analog front-end samples the difference between the analog input in
and the reference controlled by the digital codes sel_dac
. The comparator then determines the polarity of this difference and delivers the result comp_out
to the digital finite-state machine. Based on this polarity, the digital finite-state machine sets the next value of the digital codes sel_dac
via the successive approximation algorithm and produces the final digital output out
when its sequence is over.
Input/Output Terminals
Name | I/O | Type | Description |
out[5:0] | output | bit | digital output |
clk | input | xbit | sample-and-hold clock |
in | input | xreal | analog input |
List of Children Cells
ADC_SuccApproxADC_FSM : A finite-state machine for a successive approximation register ADC |
ADC_SuccApproxADC_Frontend : An analog front-end for a successive approximation register ADC |
List of Testbenches
tb_check_sineinput : A testbench for checking the basic operation of an ADC with a sinusoidal input |
tb_check_sineinput : A testbench for checking the basic operation of an ADC with a sinusoidal input
This testbench checks the basic operation of an ADC, by applying a sinusoidal signal to the input in
of the ADC and observing its digital outputs out
. The testbench drives the input clk
with a periodic clock.
The ADC is expected to produce a digital output corresponding to the same-frequency sinusoid.
Simulation Results
Figure. input and output of an ADC.