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Modeling a digital phase interpolator with nonlinear characteristics
The tutorial titled "Modeling and Simulation of High-Speed I/O Interfaces with XMODEL" describes the model of a phase-interpolator based clock-and-data recovery loop (PI-CDR). However, the model of the digital phase interpolator (PI) presented there has perfect linearity. That is, its interpolation weight varies linearly with the digital input code.
A realistic PI may have non-zero differential and integral nonlinearities (DNL and INL) and I want to simulate their effects on the CDR performance. Can you show me how to model a digital phase interpolator with arbitrary nonlinear characteristics?
Of course. All you need is to realize that you can model a digital-to-analog converter (DAC) with arbitrary DNL and INL characteristics using an ideal DAC followed by a nonlinear function. In XMODEL, the nonlinear function can be modeled using a 'pwl_func' primitive.
The sandbox.PI_phdac:schematic cellview shown on the left is the baseline model of the phase DAC with an ideal phase interpolator. It takes a set of 8-phase clocks as the inputs and selects two adjacent phases among them using a set of two multiplexers. The two selected clocks, 'ck_e' and 'ck_o', are then mixed with a weight controlled by the digital input 'mix<3:0>' to produce the output clock. To do so, an ideal DAC converts the digital input to an analog value 'weight', which in turn controls the interpolation weight of the 'interp_var_xbit' primitive, performing the phase interpolation.
The sandbox.PI_phdac_NL:schematic cellview shown on the right is the phase DAC model with a nonlinear phase interpolator. Notice that all we did was to insert a 'pwl_func' primitive between the DAC and 'interp_var_xbit' primitive. This 'pwl_func' primitive can describe arbitrary DNL and INL errors present in the conversion from the digital input 'mix<3:0>' to the analog output 'weight'. In this example, we defined the following piecewise-linear function to describe a nonlinear mapping from the ideal 'weight0' to the realistic 'weight'.
To demonstrate the nonlinearity of this phase interpolator model, we set up a testbench cellview sandbox.PI_top:tb_check. It tries to synthesize two clock phases using the phase DAC model with nonlinearity (PI_phdac_NL) and the phase DAC model without nonlinearity (PI_phdac) while incrementally varying the value of the digital control input 'ctrl<5:0>'.
Shown below are the simulated waveforms of the digital control input 'ctrl<5:0>' and the phases of the two output clocks. As expected, the phase of the clock produced by PI_phdac ('phase_out0.phase') varies along a straight line, implying perfect linearity. On the other hand, the phase of the clock produced by PI_phdac_NL ('phase_out1.phase') has a nonlinear trajectory, repeating the DNL/INL pattern defined by the 'pwl_func' primitive.
Attachment: phinterp_20240529.tar.gz
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비선형 특성을 가진 디지털 위상보간기 모델링하기
"XMODEL을 활용한 고속 I/O 인터페이스 모델링 및 시뮬레이션" 튜토리얼을 보면 위상보간기 기반의 클록 및 데이터 복원루프(phase-interpolator based clock-and-data recovery; PI-CDR)의 모델에 대한 설명이 있습니다. 하지만, 거기서 설명된 디지털 위상보간기(phase interpolator; PI) 모델은 완벽한 선형성을 가정하고 있습니다. 다시 말해, 보간 가중치가 입력 디지털 코드에 따라 선형적으로만 변화합니다.
하지만, 실제 위상보간기 회로는 차동비선형 (differential nonlinearity; DNL) 오차 및 적분비선형 (integral nonlinearity; INL) 오차를 가질 수 있습니다. 그리고 그런 비선형 특성이 CDR 성능에 미치는 영향을 시뮬레이션해보고 싶습니다. 임의의 비선형 특성을 가진 디지털 위상보간기를 모델링하는 방법을 보여줄 수 있나요?
Of course. All you need is to realize that you can model a digital-to-analog converter (DAC) with arbitrary DNL and INL characteristics using an ideal DAC followed by a nonlinear function. In XMODEL, the nonlinear function can be modeled using a 'pwl_func' primitive.
The sandbox.PI_phdac:schematic cellview shown on the left is the baseline model of the phase DAC with an ideal phase interpolator. It takes a set of 8-phase clocks as the inputs and selects two adjacent phases among them using a set of two multiplexers. The two selected clocks, 'ck_e' and 'ck_o', are then mixed with a weight controlled by the digital input 'mix<3:0>' to produce the output clock. To do so, an ideal DAC converts the digital input to an analog value 'weight', which in turn controls the interpolation weight of the 'interp_var_xbit' primitive, performing the phase interpolation.
The sandbox.PI_phdac_NL:schematic cellview shown on the right is the phase DAC model with a nonlinear phase interpolator. Notice that all we did was to insert a 'pwl_func' primitive between the DAC and 'interp_var_xbit' primitive. This 'pwl_func' primitive can describe arbitrary DNL and INL errors present in the conversion from the digital input 'mix<3:0>' to the analog output 'weight'. In this example, we defined the following piecewise-linear function to describe a nonlinear mapping from the ideal 'weight0' to the realistic 'weight'.
To demonstrate the nonlinearity of this phase interpolator model, we set up a testbench cellview sandbox.PI_top:tb_check. It tries to synthesize two clock phases using the phase DAC model with nonlinearity (PI_phdac_NL) and the phase DAC model without nonlinearity (PI_phdac) while incrementally varying the value of the digital control input 'ctrl<5:0>'.
Shown below are the simulated waveforms of the digital control input 'ctrl<5:0>' and the phases of the two output clocks. As expected, the phase of the clock produced by PI_phdac ('phase_out0.phase') varies along a straight line, implying perfect linearity. On the other hand, the phase of the clock produced by PI_phdac_NL ('phase_out1.phase') has a nonlinear trajectory, repeating the DNL/INL pattern defined by the 'pwl_func' primitive.
Attachment: phinterp_20240529.tar.gz
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