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CommunityCategory: XMODELProfiling simulation runtimes in NCVerilog/Xcelium
SA Support Team Staff asked 4 years ago

I am simulating a rather large system model with XMODEL, using Cadence Xcelium as the host SystemVerilog simulator. To improve the current simulation runtime, I'd like to know which part of the model is consuming the most time. Is there a way to measure the time consumed by each module instance during the simulation?

1 Answers
Best Answer
SA Support Team Staff answered 4 years ago

Yes, there is. It's called "profiling". Most SystemVerilog simulators are equipped with a profiling capability and NCVerilog/Xcelium is no exception. As one of the reports generated by profiling is the list of times consumed by the individual module instances, you can use this result to find any bottlenecks in your models.

To enable profiling, add the Cadence-specific option '+iprof' to the 'xmodel' command using the '--elab-option'. For more information on this '--elab-option', please refer to this Q&A posting. If you are using the NCVerilog or Xcelium commands directly to run the simulation, you can add the '+iprof' option to the command performing the elaboration.

xmodel <other options> --elab-option +iprof --

Now, run the simulation. By default, the simulator creates a result directory named 'iprof_report_dir' to store the profiling data.

Here is a simple way to generate a report file named 'inst.summary' using the 'iprof' command in a batch mode:

iprof -batch
iprof> summary -inst -out inst.summary

Below is an excerpt of the output file 'inst.summary'. As you can see, it lists the percentage of the runtime consumed by each instance in the design hierarchy.

Cumulative Grade %   Self     Instance's Hierarchical name
-------------------  -----    -----------------------------
48.95 %              0 %      tb_run.TB_TOP_5G
48.95 %              0 %      tb_run
47.02 %              0.09 %   tb_run.TB_TOP_5G.RX_ABB
24.5 %               0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_LB2
17.63 %              0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1
17.56 %              0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1.RX_ABB_PGA_Q
17.47 %              0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1.RX_ABB_PGA_Q.RX_ENV_DET
15.5 %               0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_LB2.RX_ABB_PGA_I
15.5 %               0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_LB2.RX_ABB_PGA_I.RX_ENV_DET
15.47 %              0.08 %   tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1.RX_ABB_PGA_Q.RX_ENV_DET.XP10
...

The 'iprof' program from Cadence also offers a GUI mode that allows you to browse the profiling results in an interactive fashion. To run 'iprof' in this GUI mode, use the following command:

iprof -load iprof_report_dir/prof_cpu

On the welcome panel, click the 'Analyze Profiling Data' button. You will get a graphical view of the profiling results. For more information on 'iprof', please refer to the Cadence documentations.

Note that the 'iprof' program can't provide detailed analysis for the parts described by the circuit primitives of XMODEL. On profiling the simulation times of your circuit-level models (CLMs), refer to an alternate method described by this Q&A posting.

Please refer to this Q&A posting if you'd like to learn how to profile your simulation running in VCS.

SA Support Team Staff asked 4 years ago

Cadence Xcelium과 XMODEL을 사용해 비교적 크고 복잡한 시스템 모델을 시뮬레이션하고 있습니다. 현재 시뮬레이션 수행시간을 더 개선하기 위해서, 모델의 어떤 부분이 가장 많은 시간을 소모하고 있는지를 알고 싶습니다. 시뮬레이션 동안 각 모듈 인스턴스들이 소모하는 시간을 측정하는 방법이 있나요?

1 Answers
Best Answer
SA Support Team Staff answered 4 years ago

Yes, there is. It's called "profiling". Most SystemVerilog simulators are equipped with a profiling capability and NCVerilog/Xcelium is no exception. As one of the reports generated by profiling is the list of times consumed by the individual module instances, you can use this result to find any bottlenecks in your models.

To enable profiling, add the Cadence-specific option '+iprof' to the 'xmodel' command using the '--elab-option'. For more information on this '--elab-option', please refer to this Q&A posting. If you are using the NCVerilog or Xcelium commands directly to run the simulation, you can add the '+iprof' option to the command performing the elaboration.

xmodel <other options> --elab-option +iprof --

Now, run the simulation. By default, the simulator creates a result directory named 'iprof_report_dir' to store the profiling data.

Here is a simple way to generate a report file named 'inst.summary' using the 'iprof' command in a batch mode:

iprof -batch
iprof> summary -inst -out inst.summary

Below is an excerpt of the output file 'inst.summary'. As you can see, it lists the percentage of the runtime consumed by each instance in the design hierarchy.

Cumulative Grade %   Self     Instance's Hierarchical name
-------------------  -----    -----------------------------
48.95 %              0 %      tb_run.TB_TOP_5G
48.95 %              0 %      tb_run
47.02 %              0.09 %   tb_run.TB_TOP_5G.RX_ABB
24.5 %               0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_LB2
17.63 %              0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1
17.56 %              0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1.RX_ABB_PGA_Q
17.47 %              0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1.RX_ABB_PGA_Q.RX_ENV_DET
15.5 %               0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_LB2.RX_ABB_PGA_I
15.5 %               0 %      tb_run.TB_TOP_5G.RX_ABB.RX_ABB_LB2.RX_ABB_PGA_I.RX_ENV_DET
15.47 %              0.08 %   tb_run.TB_TOP_5G.RX_ABB.RX_ABB_HB1.RX_ABB_PGA_Q.RX_ENV_DET.XP10
...

The 'iprof' program from Cadence also offers a GUI mode that allows you to browse the profiling results in an interactive fashion. To run 'iprof' in this GUI mode, use the following command:

iprof -load iprof_report_dir/prof_cpu

On the welcome panel, click the 'Analyze Profiling Data' button. You will get a graphical view of the profiling results. For more information on 'iprof', please refer to the Cadence documentations.

Note that the 'iprof' program can't provide detailed analysis for the parts described by the circuit primitives of XMODEL. On profiling the simulation times of your circuit-level models (CLMs), refer to an alternate method described by this Q&A posting.

Please refer to this Q&A posting if you'd like to learn how to profile your simulation running in VCS.