Modeling and Simulation of High-Speed I/O Interfaces in XMODEL
Overview
This tutorial covers how to model the key components of high-speed links such as channels, transceivers, equalizers, and clock generation/recovery circuits and simulate the overall system performance metrics such as bit-error rates (BERs), eye diagrams, jitter tolerance curves, etc. For instance, the tutorial covers:
Lecture Notes
- Lecture #01: Modeling and simulation of high-speed I/O interfaces with XMODEL
- Lecture #02: Getting started with XMODEL and GLISTER
- Lecture #03: Transmission line basics and its simulation
- Lecture #04: High-speed transmitter and receiver modeling
- Lecture #05: Serializer and deserializer modeling
- Lecture #06: Channel equalization and its simulation
- Lecture #07: Modeling and simulation of charge-pump phase-locked loop (PLL)
- Lecture #08: Clock-and-data recovery (CDR) loop modeling
- Lecture #09: BER Analysis of High-Speed I/O Interfaces in XMODEL
How To Get Started
1. Install the latest XMODEL package as explained in the XMODEL Installation Guide.
2. Properly setup your Unix shell & Cadence® Virtuoso® environments as explained in the XMODEL Installation Guide or XMODEL Setup Summary documents.
3. Copy the tutorial files to your local directories, for instance:
cp -R ${XMODEL_HOME}/tutorial/xmodel_hslink ~/xmodel_hslink
4. Set additional environment variables for the tutorials by sourcing the setup files located in the etc/ directory.
For instance, on bash-like shells:
cd ~/xmodel_hslink source etc/setup.bashrc
And on csh-like shells:
cd ~/xmodel_hslink source etc/setup.cshrc
You may need to modify these setup files according to your own environment.
5. Start the Cadence® Virtuoso® session:
cd cadence virtuoso &
6. And follow the instructions in the tutorial materials in ~/xmodel_hslink/doc. Enjoy!