TDC_IdealTDC : An ideal time-to-digital converter (TDC)

A time-to-digital converter (TDC) measures the timing difference between two input signals clk_fb and clk_ref and produces the output out expressing the result in a digital format.

This ideal TDC model describes the ideal functionality of a TDC, using a clk_to_delay primitive followed by an adc primitive. That is, the clk_to_delay primitive measures the delay between the two input clocks clk_fb and clk_ref and the adc primitive digitizes the delay into a digital output. The parameters delay_min and delay_lsb define the range and resolution of the delay being digitized. The output is expressed in a two’s complement format by adding an offset of -8 (4’b1000) to the adc primitive’s raw output.

Input/Output Terminals

Name	I/O	Type	Description
out[3:0]	output	bit	output
clk_fb	input	xbit	feedback clock
clk_ref	input	xbit	reference clock

Parameters

Name	Type	Default	Description
out_min	int	-8	minimum output range
delay_lsb	real	64p	delay resolution
delay_min	real	delay_lsb*out_min	minimum delay range

List of Testbenches

tb_meas_tfdc : A testbench for measuring the timing error vs. output transfer characteristics of a time-to-digital converter (TDC)

tb_meas_tfdc : A testbench for measuring the timing error vs. output transfer characteristics of a time-to-digital converter (TDC)

This testbench measures the timing error vs. output transfer characteristics of a time-to-digital converter (TDC) by gradually changing the timing difference applied to the TDC’s two inputs. A probe_dc primitive sweeps the timing error and measures the TDC’s digital output assuming it is in two’s complement representation. The result shows the digital output code produced for each interval of the input timing difference.

Simulation Results