PLL_DigitalPLL_LoopFilter : A digital loop filter for digitally-controlled PLL

A digital loop filter for a digitally-controlled PLL processes the digital phase error information provided by the time-to-digital converter (TDC) and determines the digital code fed to the digitally-controlled oscillator.

This digital loop filter model describes a digital controller with a proportional gain and an integral gain, set by the parameters Kp and Ki, respectively. The controller takes a signed 4-bit input in[3:0] and produces an unsigned 12-bit output out[11:0] by combining the current value of the input and the accumulated value of the past inputs each scaled by the proportional and integral gains, respectively. The model is described in Verilog.

Note that this model describes only the most basic functionality of the digital loop filter and is suitable only for behavioral simulations. A more practical implementation may include timing synchronization, decimation, and ways to reduce effective latency of the loop filter. Furthermore, it is desirable to model such a digital controller in synthesizable Verilog, so that it can be synthesized into gate-level netlists once its functionality is verified.

`include "xmodel.h"

module PLL_DigitalPLL_LoopFilter #(
    parameter Kp=32,                        // proportional gain
    parameter Ki=1,                         // integral gain
    parameter init_value=12'b1000_0000_0000 // initial ctrl value
)(
    input signed [3:0] in,                  // timing error input
    output reg [11:0] out,                  // control output
    input clk,                              // triggering clock
    input reset                             // reset signal
);

    // variables
    reg     [11:0]  acc;
    wire    [11:0]  in_ext;

    // digital filter
    assign in_ext = {{8{in[3]}}, in};

    always @(posedge clk or reset) begin
        if (reset) begin
            acc <= init_value;
        end
        else begin
            acc <= acc + Ki*in_ext;
        end
    end

    always @(reset or acc or in_ext) begin
        if (reset) begin
            out = init_value;
        end
        else begin
            out = Kp*in_ext + acc;
        end
    end

endmodule

Input/Output Terminals

Name	I/O	Type	Description
in[3:0]	input	wire	timing error input
out[11:0]	output	reg	control output
clk	input	wire	triggering clock
reset	input	wire	reset signal

Parameters

Name	Type	Default	Description
Kp	integer	32	proportional gain
Ki	integer	1	integral gain
init_value	integer	12’b1000_0000_0000	initial ctrl value