DPC_PhaseDAC_Encoder : An encoder logic for a phase-domain digital-to-analog converter (DAC)
An encoder logic converts one digital representation to another. This particular encoder logic for a phase-domain digital-to-analog converter (DAC) converts the 6-bit input code in[5:0]
, indicating the phase position spanning from 0 to 360 degrees with uniform steps, to a set of output codes sel_e[1:0]
, sel_o[1:0]
, and mix[2:0]
, each of which corresponds to the inputs to the even and odd phase multiplexers and phase interpolator, respectively, for the phase-domain DAC to produce the output clock with the desired phase.
This encoder model is described in pure Verilog. The outputs are retimed with the rising edge of the phase inpterpolator output clock clk
to prevent them from switching during the output clock transition.
module DPC_PhaseDAC_Encoder ( output reg [1:0] sel_e, // selection for even mux output reg [1:0] sel_o, // selection for odd mux output reg [2:0] mix, // weight for phase interpolator input [5:0] in, // input code input clk // input clock ); wire [1:0] rsel_e, rsel_o; wire [2:0] rmix; // encoder logic assign rsel_e = in[5:4] + in[3]; assign rsel_o = in[5:4]; assign rmix = in[3] ? ~in[2:0] : in[2:0]; // retimers initial begin sel_e = 2'b0; sel_o = 2'b0; mix = 3'b0; end always @(posedge clk) begin sel_e = rsel_e; sel_o = rsel_o; mix = rmix; end endmodule
Input/Output Terminals
Name | I/O | Type | Description |
sel_e[1:0] | output | reg | selection for even mux |
sel_o[1:0] | output | reg | selection for odd mux |
mix[2:0] | output | reg | weight for phase interpolator |
in[5:0] | input | wire | input code |
clk | input | wire | input clock |