DLN_LinearVCDL4DO2C : A voltage-controlled delay line (VCDL) with dual control inputs, linear V-to-D characteristic, and 4 differential outputs
A dual-control-input voltage-controlled delay line (VCDL) controls the delay between the input clock and output clock with two control voltages vctrl1
and vctrl2
. It is typically implemented as a chain of variable delay elements.
This particular VCDL model is a chain of four identical variable delay elements, which collectively produce 4 pairs of complementary clocks clk_out
and clk_outb
with equal delay spacings. When the total delay through the delay line is equal to a half clock period, the output clocks clk_out
and clk_outb
become the eight multi-phase clocks that span 360 degrees with uniform phase spacings.
This VCDL model assumes that its delay varies linearly with the control voltages vctrl1
and vctrl2
, that is, delay=delay0+Kd1*(vctrl1-vctrl1_0)+Kd2*(vctrl2-vctrl2_0)
, where the parameter delay0
is the nominal delay of the VCDL when vctrl1
and vctrl2
are at their nominal values defined by the parameters vctrl1_0
and vctrl2_0
, respectively, and the parameters Kd1
and Kd2
are the VCDL gains, i.e., the rate of change in the VCDL delay with respect to the changes in vctrl1
and vctrl2
, respectively. The delay of the delay line may have the maximum and minimum limits, which are set by the parameters delay_max
and delay_min
, respectively.
Input/Output Terminals
Name | I/O | Type | Description |
clk_out[3:0] | output | xbit | multi-phase output clocks (pos) |
clk_outb[3:0] | output | xbit | multi-phase output clocks (neg) |
clk_in | input | xbit | input clock |
vctrl1 | input | xreal | control voltage #1 |
vctrl2 | input | xreal | control voltage #2 |
Parameters
Name | Type | Default | Description |
delay0 | real | 3.2n | delay at nominal vctrl values (s) |
vctrl1_0 | real | 0.5 | nominal value for vctrl1 (V) |
vctrl2_0 | real | 0.5 | nominal value for vctrl2 (V) |
Kd1 | real | -12n | delay control gain for vctrl1 (s/V) |
Kd2 | real | -6n | delay control gain for vctrl2 (s/V) |
delay_max | real | 5.6n | maximum limit on delay (s) |
delay_min | real | 0.8n | minimum limit on delay (s) |
List of Children Cells
BLK_DelayElement2C : A variable delay element with dual control inputs and linear V-to-D characteristics |
List of Testbenches
tb_check : A testbench for checking the basic operation of a dual-control-input voltage-controlled delay line (VCDL) |
tb_meas_tfdc : A testbench for measuring the voltage-to-delay characteristics of a voltage-controlled delay line (VCDL) |
tb_check : A testbench for checking the basic operation of a dual-control-input voltage-controlled delay line (VCDL)
This testbench checks the basic operation of a dual-control-input voltage-controlled delay line (VCDL) by varying the values of the two control voltages and observing the resulting delay of the delay line. For the first 100 cycles, the control voltages vctrl1
and vctrl2
are held at their nominal values that keep the delay equal to a half clock period. For the second 100 cycles, vctrl1
changes from 1 to 0V and for the third 100 cycles, vctrl2
changes from 1 to 0V. For the last 100 cycles, vctrl1
and vctrl2
change simultaneously, from 1 to 0 and from 0 to 1, respectively.
Simulation Results
Figure. the delay of the VCDL varying with the changes in vctrl1
and vctrl2
.
Figure. the input and 8-phase output clocks at the locked state.
tb_meas_tfdc : A testbench for measuring the voltage-to-delay characteristics of a voltage-controlled delay line (VCDL)
This testbench measures the voltage-to-delay characteristics of a voltage-controlled delay line (VCDL), by gradually varying the control voltage vctrl1
and measuring its delay. This vctrl1-to-delay transfer characteristic is measured for three different values of vctrl2
. The resulting transfer characteristics are expected to show the delay varying as the model equation: delay=delay_0+Kd1*(vctrl1-vctrl1_0)+Kd2*(vctrl2-vctrl2_0)
.
Simulation Results
Figure. the voltage-to-delay characteristic of the VCDL.