BLK_DelayElement : A variable delay element with a linear V-to-D characteristic
A variable delay element propagates an input clock in
to an output clock out
with a variable amount of delay.
In this particular model, the delay is controlled by a control voltage vctrl
via a linear V-to-D characteristic. That is:
delay = delay0 + Kd*(vctrl-vctrl0)
where the parameter delay0
is the nominal delay when vctrl
is at its nominal value (the parameter vctrl0
) and the parameter Kd
is the control gain of the variable delay element, defined as the rate of change in the delay with respect to the vctrl
change. In addition, the delay element may have the maximum and minimum limits, which are set by the parameters delay_max
and delay_min
, respectively.
This variable delay element model consists of a poly_func
, limit
, and delay_to_clk
primitives, where the poly_func
and limit
primitives calculate a delay value from the vctrl
input and the delay_to_clk
primitive produces the output clock out
by delaying the input clock in
with the calculated delay amount.
Input/Output Terminals
Name | I/O | Type | Description |
out | output | xbit | output clock |
in | input | xbit | input clock |
vctrl | input | xreal | control voltage |
Parameters
Name | Type | Default | Description |
vctrl0 | real | 0.5 | nominal vctrl value (V) |
delay0 | real | 0.8n | delay at nominal vctrl value (s) |
Kd | real | -3n | delay control gain (s/V) |
delay_max | real | 1.4n | maximum limit on delay (s) |
delay_min | real | 0.2n | minimum limit on delay (s) |
List of Testbenches
tb_check : A testbench for checking the basic operation of a variable delay element |
tb_meas_tfdc : A testbench for measuring the voltage-to-delay (V-to-D) characteristics of a variable delay element |
tb_check : A testbench for checking the basic operation of a variable delay element
This testbench checks the basic functionality of a variable delay element by feeding a constant-frequency clock and varying its control voltage. The measured input-to-output delay of the variable delay element is expected to change according to its V-to-D characteristics.
Simulation Results
Figure. input and output waveforms.
tb_meas_tfdc : A testbench for measuring the voltage-to-delay (V-to-D) characteristics of a variable delay element
This testbench measures the voltage-to-delay (V-to-D) characteristics of a variable delay element, by gradually varying the control voltage vctrl
and measuring the delay. The resulting DC transfer characteristics correspond to the V-to-D characteristics of interest.
Simulation Results
Figure. the voltage-to-delay characteristics.