Checking if a signal has stayed within a desired range for a certain period of time

Certainly. The sandbox.chk_settle:schematic cellview shown below and included in the attached package demonstrates how one can determine whether an analog signal has settled within a specified range for a given period of time. The minimum and maximum values of this range are defined by the real-type array parameter 'range[0:1]', while the minimum duration that the signal must remain within this range is specified by the parameter 't_hold'.

First, a pair of 'slice' primitives compare the input signal 'vin' with the minimum and maximum values of the specified range, determining whether the signal is too low ('low') or too high ('high'), respectively. Then, a 'nor_xbit' primitive combines these results to generate a signal called 'valid', which indicates whether 'vin' is within the specified range. Note that this 'nor_xbit' primitive has a delay of 't_hold', and due to its inertial delay behavior, 'valid' will be asserted to 1 only when both 'low' and 'high' remain at 0 for the duration of 't_hold'. Finally, the output is gated with the enable input 'en', ensuring that the final output is immediately de-asserted when 'en' becomes 0.

The sandbox.tb_chk_settle:schematic cellview is prepared to show how this checker operates. The 'en' signal periodically toggles between 0 and 1, while the LDO model outputs a voltage of 0.8V when 'en' = 1 and 0.0V when 'en' = 0, exhibiting some transient behavior during transitions. The 'chk_settle' cell described above monitors this output voltage 'vout' and asserts the signal 'settle' when 'vout' remains between 0.79V and 0.81V for a duration of 50ns.

For your information, the sandbox.ldo_model:schematic cellview shown below emulates the transient behavior of the LDO regulator output when it is enabled or disabled. The 'transition' primitive sets the final output voltage to 0.8V when 'en' = 1 and to 0.0V when 'en' = 0. The 'filter' primitive models the transient response as an underdamped response of a second-order low-pass system.

Shown below are the simulated waveforms obtained using the 'tb_chk_settle' testbench schematic. The signal 'settle' goes high when the LDO output voltage 'vout' remains within the specified range of [0.79, 0.81] for a duration of 50ns, and it returns low immediately when the 'en' signal becomes low.

Attachment: chk_settle_20251107.tar.gz