Can GLISTER netlist model schematics with Real-Number Model (RNM) type ports?

Yes, you can. First, you can enable the GLISTER support for real-number model (RNM) nettypes by adding the following lines in your .cdsinit initialization file.

;------------------------------------------------------------
; GLISTER support for real-number model (RNM) nettypes
;------------------------------------------------------------

xmodelSetSigTypeCompatReal( 
    "wreal1driver" 
    "wreal4state" 
    "wrealsum" 
    "wrealavg"
    "wrealmax"
    "wrealmin"
)

The xmodelSetSigTypeCompatReal( <type1> <type2> … ) is a GLISTER API function that sets a list of signal types compatible with real. Similarly, you can use xmodelAddSigTypeCompatReal( <type1> <type2> … ) to add additional signal types to the current list.

For instance, the attached package contains a cellview named sandbox.driver_wreal:schematic, which is simply a sin_gen primitive driving a sinusoidal signal to its inputOutput port named 'out'. When you open the Edit Object Properties dialog window for the port, you can notice that the XMODEL Signal Type field has more choices, including the RNM nettypes defined using xmodelSetSigTypeCompatReal(). We've chosen 'wrealavg' for this example. When we use multiple of these cells driving a shared wrealavg-type net, it will take the average value of the values driven by the individual driver cells. This is also the reason why the port is defined as a bidirectional inputOutput port.

Shown below is the SystemVerilog file netlisted from this schematic by GLISTER. Note that the port 'out' is declared as a bidirectional inout port with the type 'wrealavg', as intended. Also, GLISTER automatically inserts the xreal_to_real connect primitive that converts the xreal-type output of the sin_gen primitive to a real-type signal, and the assign statement that assigns this real-type signal to the wrealavg-type inout port, 'out'.

Another cellview named sandbox.receiver_wreal:schematic demonstrates that an input port can also be an RNM nettype. It is basically a buffer primitive that propagates a wrealavg-type input to an xreal-type output as-is. Again, the XMODEL Signal Type of the input port is set to 'wrealavg' using the Edit Object Properties dialog.

Also, the SystemVerilog file netlisted from this schematic is shown below. The input port 'in' is declared as 'wrealavg' type, and GLISTER inserts a real_to_xreal connect primitive that converts the wrealavg-type input to an xreal-type signal, driving the buffer primitive. The buffer primitive then drives the xreal-type output, 'out'.

The cellview sandbox.tb_wreal:schematic combines the driver_wreal and receiver_wreal cells. Each of the four driver_wreal cells drives a sinusoid with the frequency of 100, 300, 500, and 700MHz and the amplitude of 1.0, 1.0/3, 1.0/5, and 1.0/7, respectively. Since these are the Fourier components of a 100MHz square-wave signal, we expect the wrealavg-type signal 'avg' shorting the four driver_wreal cell outputs and the xreal-type signal 'out' propagated by the receiver_wreal cell to take the waveforms close to a square wave.

Shown below is the SystemVerilog file netlisted from this schematic cellview. Note that the signal 'avg' is defined as 'wrealavg' type and connects between the outputs of the four driver_wreal cells and the input of the receiver_wreal cell.

The simulated waveforms of the 'avg' and 'out' signals are shown below. As expected, the signals' waveforms look similar to a 100MHz square wave.

Note that each of the SystemVerilog files listed earlier contains an import statement at the beginning (import cds_rnm_pkg::*;). In fact, VCS, Xcelium, and Questa define the RNM nettypes in different packages, so the required import statement depends on the SystemVerilog simulator. This can be achieved by adding the following lines to the .cdsinit initialization file to define the simulator-specific module file headers. Please refer to this Q&A post for further details.

xmodelModuleFileHeader->vcs = strcat(
    "`include \"xmodel.h\"\n"
    "import snps_msv_nettype_pkg::*;\n"
)
xmodelModuleFileHeader->xcelium = strcat(
    "`include \"xmodel.h\"\n"
    "import cds_rnm_pkg::*;\n"
)
xmodelModuleFileHeader->questa = strcat(
    "`include \"xmodel.h\"\n"
    "import mgc_rnm_pkg::*;\n"
)

Alternatively, one can provide the '--rnm' option when running the XMODEL simulation as shown below. This option enables the import of the simulator-specific RNM package within the xmodel.h header file.

You may have noticed the wrealavg-type signal 'avg' generates many events, yet its accuracy remains somewhat unsatisfactory. In fact, to achieve the simulated waveforms shown earlier, we had to tighten the tolerance of the xreal_to_real connect primitives, by adding the following lines in the .cdsinit file:

;------------------------------------------------------------
; defining tolerance for xreal_to_real connectors
;------------------------------------------------------------

xmodelConvXrealToRealAbsTol = 1e-4
xmodelConvXrealToRealRelTol = 1e-4

Still, the resulting accuracy is not what we expect, due to the limited tolerance set in the wrealavg resolution function.

On the other hand, the cellview sandbox.tb_xreal:schematic shows the XMODEL way of producing the average value of the multiple driver outputs. Each driver cell, sandbox.driver_xreal:schematic, is basically a sin_gen primitive driving an xreal-type output via a resistor primitive connected in series. When the outputs of four driver_xreal cells are shorted together, the resulting voltage naturally takes the average of the four driver outputs via the 4-input resistor divider.

And shown below are the simulated waveforms of the 'avg' and 'out' signals, corresponding to the signals with the same names in the previous example using the RNM nettype. Note that the waveforms are 100% accurate. Furthermore, the entire simulation produces only a single event at time 0. XMODEL is a simpler yet more effective way of modeling various analog circuit effects and simulating them efficiently in SystemVerilog.

Attachment: UDM_wreal_20250820.tar.gz