Categories

Community › Category: MODELZEN › Supporting SPICE netlisters that do not add "inh_" prefix to inherited nets

MODELZEN

Supporting SPICE netlisters that do not add "inh_" prefix to inherited nets

SA Support Team Staff 2025-08-21

My design uses inherited nets for supply and ground. For example, consider this chain of inverters whose supply and ground are connected via inherited nets, named 'pvdd' and 'pvss'.

When I run MODELZEN to extract models from this circuit, I get the following error:

*** ERROR: The terminal 'inh_pvdd' of cell 'inv' defined in the design information file is not found in the port definition of the netlist: in, out, pvdd, pvss.

It complains about the terminal named 'inh_pvdd' not being found in the SPICE netlist. For your information, the following is the SPICE netlist extracted from the circuit schematics. Indeed, it does not contain a terminal named 'inh_pvdd'. 

.subckt inv in out pvdd pvss
m0 out in pvss pvss nmos L=90e-9 W=500e-9
m1 out in pvdd pvdd pmos L=90e-9 W=1e-6
.ends inv

xu3 n2 out vdd! vss! inv
xu2 n1 n2 vdd! vss! inv
xu1 in n1 vdd! vss! Inv

Where did the name 'inh_pvdd' come from? How do I address this problem?

1 Answers
Vote Up 0 Vote Down
SA Support Team Staff 2025-08-21

It appears that you are using a netlister other than the one with Cadence ADE to extract the SPICE netlist from the schematics. Or, it is possible that you are using a legacy netlister (e.g. 'si'). The Cadence ADE netlister would produce a SPICE netlist from your schematics as shown below:

.subckt inv in out inh_pvdd inh_pvss
m0 out in inh_pvss inh_pvss nmos L=90e-9 W=500e-9
m1 out in inh_pvdd inh_pvdd pmos L=90e-9 W=1e-6
.ends inv

xu3 n2 out vdd! vss! inv
xu2 n1 n2 vdd! vss! inv
xu1 in n1 vdd! vss! inv

Note the prefix 'inh_' added to all the terminal names derived from the inherited nets. Because of this, when GLISTER extracts the design information file (the 'dbinfo' file) listing various MODELZEN properties annotated on the design schematics, it adds the same 'inh_' prefix to the terminal names derived from the inherited nets.

But in your case, your netlister didn't add the 'inh_' prefix and MODELZEN found a mismatch between the name 'pvdd' used in the netlist file and 'inh_pvdd' used in the design information file.

To address this mismatch, you just need to tell GLISTER not to add the 'inh_' prefix when extracting the design information file from the schematics. Since the SKILL variable 'modelzenInheritedNetPrefix' defines this prefix string, you just need to set it to an empty string.

modelzenInheritedNetPrefix = ""

You can include this line in the .cdsinit file to make this setup persistent across sessions.