Mapping ‘analogLib’ global symbols to different signal names

SA Support Team Staff 2025-08-01

I know GLISTER can netlist a schematic composed with 'analogLib' components (see this Q&A post) into a SystemVerilog model. For example, it can netlist the following schematic, composed with the instances of 'vcc', 'res', 'cap', and 'gnd' cells of the 'analogLib' library, into a SystemVerilog model using the equivalent XMODEL primitives, such as 'resistor' and 'capacitor'.

Note that the global symbol named 'vcc' is netlisted as a signal named '`global_vcc', which is a macro defined as '$root.XMODEL_global.vcc'. XMODEL defines a global net as a variable within a top-level module named 'XMODEL_global'. In a similar fashion, the other global symbol named 'gnd' is netlisted as '`ground', which is another macro defined as '$root.XMODEL_global.ground'.

What if I have my own top-level module named 'my_global' that contains a different list of global net variables, and I want the 'vcc' symbol to be netlisted as '$root.my_global.vcc' instead of '`global_vcc'? Is there a way to customize the variable name for each global supply symbol?

1 Answers

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SA Support Team Staff 2025-08-01

Yes, there is. To give you a quick answer, you can execute the following SKILL code in the command interpreter window (CIW) of Cadence Virtuoso before netlisting the schematic. For a more permanent setup, it's better to include it in your .cdsinit initialization script.

xmodelRegisterGlobalNetMap( "vcc!" "$root.my_global.vcc" )

XMODEL releases later than 2025.07 includes the following SKILL API functions to add, remove, or list mappings between global symbols and the variable names netlisted by GLISTER:

xmodelRegisterGlobalNetMap( globalNetName mappedVarName ) : Registers a new mapping between globalNetName and mappedVarName
xmodelUnregisterGlobalNetMap( globalNetName ) : Unregisters an existing mapping of globalNetName
xmodelListGlobalNetMap() : Lists the currently-registered global net mappings