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Generating a sinusoidal signal with a resettable phase
I'd like to model a sinusoidal generator with an enable control. In other words, the generator produces a sine wave when its enable signal is 1, but stops producing it when the enable signal is 0. At first, I tried to model this generator by adding a 'switch' primitive to the output of a 'sin_gen' primitive, but the result was only half-correct. When the enable signal changes from 0 to 1, the generator starts producing the sinusoidal output again, but its initial phase depends on the time of re-activation since the switch is just passing the always-on sinusoidal signal generated by the 'sin_gen' primitive. Can you show me a way to make this new sinusoidal signal start with a known, fixed phase value (say, 0)?
Sure. There is an easy way to generate a sinusoidal signal with a resettable phase. The attached package contains a cellview named sandbox.sin_reset:schematic and its schematic is shown below.
As you can see, this sinusoidal generator model is made of just two primitives: 'integ_rst' and 'sin_func'. First, the 'integ_rst' primitive computes the time-integral of the input scaled by a constant 2π. (by setting the parameter 'scale' to 2*M_PI). So, if the input carries the frequency value of the sinusoidal signal to be generated in Hertz, the output would indicate its phase value in radians. Then, the 'sin_func' primitive on the next stage would produce the sinusoidal signal 'out' with the frequency equal to 'freq'.
The 'integ_rst' primitive also takes care of the reset operation when the 'reset' input becomes 1. With its parameter 'mode' set to 'reset', the primitive's output immediately resets to the value set by the parameter 'rst_value' when the 'reset' input becomes 1. And when the 'reset' input returns to 0, the model starts producing the sinusoidal output again with the initial phase equal to that reset value. Hence, you can define this parameter 'rst_value' with the initial phase value you want.
The testbench cellview sandbox.tb_sin_reset:schematic shown below feeds a 'freq' input that gradually increases from 200M to 400M and a 'reset' input that periodically becomes 1 to the sinusoidal generator model described above.
And the simulated waveforms shown below confirm that this model generates the sinusoidal output of which frequency is equal to the 'freq' input and of which phase gets reset to 0 whenever the 'reset' input becomes 1.
Attachment: sin_reset_20240414.tar.gz
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위상을 리셋할 수 있는 정현파 신호 생성하는 법
Enable 제어를 할 수 있는 정현파 생성기를 모델링하려고 합니다. 즉, enable 신호가 1일 때는 정현파를 생성하고, 0일때는 정현파 생성을 멈추고 싶습니다. 이를 위해 제가 처음 시도한 것은 'sin_gen' primitive의 출력에 'switch' primitive를 추가하는 것이었습니다. 하지만, 이는 절반의 성공이었습니다. Enable 신호가 0에서 1로 변할때, 이 모델은 정현파 신호를 다시 생성하기 시작했지만, 그 위상의 시작값은 그 enable된 시점에 따라 변하는 값을 가졌습니다. 그 이유는 이 모델은 내부적으로는 항상 생성되고 있는 정현파 신호를 'switch' primitive를 통해 출력으로 전파할지 말지만을 결정하고 있기 때문이었습니다. 새로운 정현파 신호가 생성될때 그 위상이 원하는 고정된 값(예를 들면, 0)에서 시작하게 하는 방법이 있을까요?
Sure. There is an easy way to generate a sinusoidal signal with a resettable phase. The attached package contains a cellview named sandbox.sin_reset:schematic and its schematic is shown below.
As you can see, this sinusoidal generator model is made of just two primitives: 'integ_rst' and 'sin_func'. First, the 'integ_rst' primitive computes the time-integral of the input scaled by a constant 2π. (by setting the parameter 'scale' to 2*M_PI). So, if the input carries the frequency value of the sinusoidal signal to be generated in Hertz, the output would indicate its phase value in radians. Then, the 'sin_func' primitive on the next stage would produce the sinusoidal signal 'out' with the frequency equal to 'freq'.
The 'integ_rst' primitive also takes care of the reset operation when the 'reset' input becomes 1. With its parameter 'mode' set to 'reset', the primitive's output immediately resets to the value set by the parameter 'rst_value' when the 'reset' input becomes 1. And when the 'reset' input returns to 0, the model starts producing the sinusoidal output again with the initial phase equal to that reset value. Hence, you can define this parameter 'rst_value' with the initial phase value you want.
The testbench cellview sandbox.tb_sin_reset:schematic shown below feeds a 'freq' input that gradually increases from 200M to 400M and a 'reset' input that periodically becomes 1 to the sinusoidal generator model described above.
And the simulated waveforms shown below confirm that this model generates the sinusoidal output of which frequency is equal to the 'freq' input and of which phase gets reset to 0 whenever the 'reset' input becomes 1.
Attachment: sin_reset_20240414.tar.gz
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