Sure. In the attached package, you will find a schematic cellview of the model (sandbox.buf_adj:schematic) that describes a digital buffer with adjustable rising and falling delays.

You may notice that it is an extension of the model you read from the previous Q&A posting. The delay from the input 'in' to the output 'out' is realized by first converting the digital input 'in' to an analog waveform 'vin' with non-zero rise and fall times and then slicing it at a threshold level 'vth' to produce the digital output 'out', using the 'transition' primitive and 'slice' primitive, respectively. One notable difference is that the threshold level 'vth' is selected as one of the two threshold levels 'vth_r' and 'vth_f', each of which is controlled by the digital control input 'ctrl_r' or 'ctrl_f' using a 'dac' primitive, respectively.

The key idea enabling the individual control of the rising delay and falling delay is with the 'select' primitive placed in the middle. Depending on whether the current value of 'in' is 1 or 0, i.e. whether the corresponding analog signal 'vin' is rising or falling, the model selects 'vth_r' or 'vth_f' as the slicing threshold, respectively. The figure above depicts that when 'vin' swings between 0.0 and 1.0 and each 'dac' primitive produces the threshold ranging from 0.001 to 0.999, the model can individually adjust the rising delay and falling delay within the ranges from 0.0 to the value equal to the rise or fall times of 'vin'. In other words, the rise and fall times of 'vin' sets the maximum rising and falling delays supported by the model.

The cellview 'sandbox.tb_buf_adj:schematic' is a testbench checking the functionality of this digital buffer model. It feeds a periodic clock input 'in' to the buffer model and sequentially varies the control inputs 'ctrl_r[3:0]' and 'ctrl_f[3:0]' during the course of the simulation. We used a simple Verilog module (the 'sandbox.ctrl_adj:xmodel' cellview) that first increments 'ctrl_r[3:0]' from 4'b0000 to 4'b1111 while 'ctrl_f[3:0]' is at 4'b0000 and then increments 'ctrl_f[3:0]' from 4'b0000 to 4'b1111 while 'ctrl_r[3:0]' is at 4'b0000. The testbench also includes a set of 'trig_posedge', 'trig_negedge', and 'meas_delay' primitives that can continuously measure the rising delays and falling delays of the buffer model.

The corresponding simulated waveforms are shown below. As explained, the control inputs 'ctrl_r[3:0]' and 'ctrl_f[3:0]' are being swept from 0 to 15 sequentially. You can observe the change in the output pulse width produced by the digital buffer as its rising and falling delays change with the control inputs. The measurement results 'delay_r' and 'delay_f' produced by the 'meas_delay' primitives confirm that the rising and falling delays are indeed being adjusted as expected.

Attachment: buf_adj_20240327.tar.gz

Sure. In the attached package, you will find a schematic cellview of the model (sandbox.buf_adj:schematic) that describes a digital buffer with adjustable rising and falling delays.

You may notice that it is an extension of the model you read from the previous Q&A posting. The delay from the input 'in' to the output 'out' is realized by first converting the digital input 'in' to an analog waveform 'vin' with non-zero rise and fall times and then slicing it at a threshold level 'vth' to produce the digital output 'out', using the 'transition' primitive and 'slice' primitive, respectively. One notable difference is that the threshold level 'vth' is selected as one of the two threshold levels 'vth_r' and 'vth_f', each of which is controlled by the digital control input 'ctrl_r' or 'ctrl_f' using a 'dac' primitive, respectively.

The key idea enabling the individual control of the rising delay and falling delay is with the 'select' primitive placed in the middle. Depending on whether the current value of 'in' is 1 or 0, i.e. whether the corresponding analog signal 'vin' is rising or falling, the model selects 'vth_r' or 'vth_f' as the slicing threshold, respectively. The figure above depicts that when 'vin' swings between 0.0 and 1.0 and each 'dac' primitive produces the threshold ranging from 0.001 to 0.999, the model can individually adjust the rising delay and falling delay within the ranges from 0.0 to the value equal to the rise or fall times of 'vin'. In other words, the rise and fall times of 'vin' sets the maximum rising and falling delays supported by the model.

The cellview 'sandbox.tb_buf_adj:schematic' is a testbench checking the functionality of this digital buffer model. It feeds a periodic clock input 'in' to the buffer model and sequentially varies the control inputs 'ctrl_r[3:0]' and 'ctrl_f[3:0]' during the course of the simulation. We used a simple Verilog module (the 'sandbox.ctrl_adj:xmodel' cellview) that first increments 'ctrl_r[3:0]' from 4'b0000 to 4'b1111 while 'ctrl_f[3:0]' is at 4'b0000 and then increments 'ctrl_f[3:0]' from 4'b0000 to 4'b1111 while 'ctrl_r[3:0]' is at 4'b0000. The testbench also includes a set of 'trig_posedge', 'trig_negedge', and 'meas_delay' primitives that can continuously measure the rising delays and falling delays of the buffer model.

The corresponding simulated waveforms are shown below. As explained, the control inputs 'ctrl_r[3:0]' and 'ctrl_f[3:0]' are being swept from 0 to 15 sequentially. You can observe the change in the output pulse width produced by the digital buffer as its rising and falling delays change with the control inputs. The measurement results 'delay_r' and 'delay_f' produced by the 'meas_delay' primitives confirm that the rising and falling delays are indeed being adjusted as expected.

Attachment: buf_adj_20240327.tar.gz