There are a variety of clocked comparator designs producing the 'done' or 'ready' signal and even each of the references you listed presents a different design. Yet, as you mentioned, most of them start with a clocked comparator latch with differential outputs and add circuits to process the state of the outputs to determine whether the decision is complete or not. So, one approach is to first model the clocked comparator latch with analog, differential outputs as described in this Q&A posting and then add the model of the circuits that produce the 'done' or 'ready' signal based on the outputs of the clocked comparator latch.

On the other hand, the module named 'comp_done' described below in SystemVerilog code format illustrates a simpler way to model such a clocked comparator. This model is included as a cellview sandbox.comp_done:xmodel in the attached package. Its output 'out' takes the digital decision output of the 'compare' primitive. On the other hand, to produce the 'done' signal, it utilizes the internal signal named 'in_reg' of the 'compare' primitive configured in a finite-aperture mode. In fact, this 'comp_done' model is a simple extension of the 'comp_latch' model described in the Q&A posting, which models a clocked comparator latch with an analog output bearing the net difference between the two differential outputs and exhibiting the reset, sampling, regeneration, and decision transients of the clocked comparator latch. In the codes listed below, the collection of primitive instances named 'COMP', 'DLY', 'SW0', 'SW1', and 'C1' corresponds to the 'comp_latch' model and its output is named 'out_r'.

Hence, the 'done' signal of the clocked comparator can be produced by detecting whether this 'out_r' signal has reached the level of '+thres_out' or '-thres_out', where 'thres_out' is the decision threshold set by the parameter 'ISF_params[4]' of the 'compare' primitive. In the 'comp_done' model, this is done with a pair of 'slice' primitives and an 'or_xbit' primitive. Each 'slice' primitive detects whether 'out_r' has reached '+thres_out' or '-thres_out', and the 'or_xbit' primitive asserts the 'done' signal when either condition is true.

module comp_done #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xbit out,                    // decision output
    output xbit done,                   // completion output
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xreal out_r;
xbit trig_d, s1, s2;

compare     #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
            COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out));
and_xbit    DLY (.in({trig, trig}), .out(trig_d));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(out_r), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(out_r), .ctrl(trig_d));
capacitor   #(.C(C)) C1 (.pos(out_r), .neg(`ground));

slice       #(.threshold(thres_out)) SL1 (.in(out_r), .in_ref(`ground), .out(s1));
slice       #(.threshold(thres_out)) SL2 (.in(`ground), .in_ref(out_r), .out(s2));
or_xbit     OR1 (.in({s1, s2}), .out(done));

endmodule

The cellview sandbox.tb_comp_done:schematic is a testbench schematic that observes the outputs 'out' and 'done' of the described 'comp_done' model while varying the net input value from -0.1 to 0.1 over a 1us period. In addition, using a pair of 'trig_posedge' primitives and a 'meas_delay' primitive, the testbench measures the clock-to-done delay of the clocked comparator, that is, the delay between the rising edge of the triggering clock 'trig' and the rising edge of the 'done' output.

The simulated waveforms of using this testbench are shown below. The clocked comparator model initiates a decision process whenever the clock has a rising edge and asserts its 'done' output when the process is complete. The waveform of the signal 'out' confirms that the clocked comparator detects the input polarity correctly, producing 0 while the net input 'in'-'in_ref' is negative and 1 while it is positive. On the other hand, the clock-to-done delay increases exponentially as the net input magnitude approaches to zero. It appears as if it has a maximum value of 500ps, but it is because the clock has a 1ns period and 50% duty-cycle. That is, the comparator cannot reach a decision within the 500ps half period when the net input is too small. In this case, the comparator model does not assert 'done'.

As you mentioned, some clocked comparator designs also employ time-out circuits, which assert the 'done' signal when a certain time period expires even though the decision has not been made yet. In asynchronous SAR ADC designs, this feature helps set the maximum bound on the time required for each comparison cycle and mitigate issues due to metastability.

The following 'comp_done_timeout' model, included as a cellview sandbox.comp_done_timeout:xmodel in the attached package, illustrates how one can add the time-out capability to the 'comp_done' model, by adding a 'transition' primitive ('TR1') and a 'slice' primitive ('SL0'). When the triggering clock 'trig' has a positive edge, the 'transition' primitive produces a ramp signal 'trig_t' that rises from -1.0 to 1.0 with the rise time of twice the time-out period ('timeout'). The 'slice' primitive instance 'SL0' detects when this 'trig_t' crosses 0.0, which would indicate the expiration of time-out period. The 3-input 'or_xbit' primitive ('OR1') asserts the 'done' output when 'SL0' detects such expiration or when 'SL1' or 'SL2' detects that 'out_r' has reached '+thres_out' or '-thres_out', respectively.

module comp_done_timeout #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real timeout = 400e-12,   // Time-out Period
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xbit out,                    // decision output
    output xbit done,                   // completion output
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xreal out_r, trig_t;
xbit trig_d, s0, s1, s2;

compare     #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
            COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out));
and_xbit    DLY (.in({trig, trig}), .out(trig_d));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(out_r), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(out_r), .ctrl(trig_d));
capacitor   #(.C(C)) C1 (.pos(out_r), .neg(`ground));

transition  #(.rise_time(2*timeout), .fall_time(0.0), .value0(-1.0), .value1(1.0))
            TR1 (.in(trig), .out(trig_t));
slice       #(.threshold(0.0)) SL0 (.in(trig_t), .in_ref(`ground), .out(s0));
slice       #(.threshold(thres_out)) SL1 (.in(out_r), .in_ref(`ground), .out(s1));
slice       #(.threshold(thres_out)) SL2 (.in(`ground), .in_ref(out_r), .out(s2));
or_xbit     #(.num_in(3)) OR1 (.in({s0, s1, s2}), .out(done));

endmodule

The simulated waveforms of the 'comp_done_timeout' model using the testbench cellview sandbox.tb_comp_done_timeout are shown below. There are two key differences with the waveforms of the previously-discussed 'comp_done' model. One is that the maximum clock-to-done delay is now 400ps, which is set by the time-out period, instead of the half period of the triggering clock. The other is that even when the net input magnitude is small and clock-to-done delay has the maximum value, the clocked comparator is still producing the valid 'done' signal. This confirms that the time-out functionality is working properly.

The attached package also includes the model of an asynchronous SAR ADC using the 'comp_done_timeout' model for its clocked comparator. The top-level cellview of the SAR ADC is saradc.saradc:schematic and the simulated waveform of its digital output responding to a full-scale sinusoidal input using the testbench saradc.tb_saradc:schematic is shown below.

Attachment: comp_latch_20230829.tar.gz

There are a variety of clocked comparator designs producing the 'done' or 'ready' signal and even each of the references you listed presents a different design. Yet, as you mentioned, most of them start with a clocked comparator latch with differential outputs and add circuits to process the state of the outputs to determine whether the decision is complete or not. So, one approach is to first model the clocked comparator latch with analog, differential outputs as described in this Q&A posting and then add the model of the circuits that produce the 'done' or 'ready' signal based on the outputs of the clocked comparator latch.

On the other hand, the module named 'comp_done' described below in SystemVerilog code format illustrates a simpler way to model such a clocked comparator. This model is included as a cellview sandbox.comp_done:xmodel in the attached package. Its output 'out' takes the digital decision output of the 'compare' primitive. On the other hand, to produce the 'done' signal, it utilizes the internal signal named 'in_reg' of the 'compare' primitive configured in a finite-aperture mode. In fact, this 'comp_done' model is a simple extension of the 'comp_latch' model described in the Q&A posting, which models a clocked comparator latch with an analog output bearing the net difference between the two differential outputs and exhibiting the reset, sampling, regeneration, and decision transients of the clocked comparator latch. In the codes listed below, the collection of primitive instances named 'COMP', 'DLY', 'SW0', 'SW1', and 'C1' corresponds to the 'comp_latch' model and its output is named 'out_r'.

Hence, the 'done' signal of the clocked comparator can be produced by detecting whether this 'out_r' signal has reached the level of '+thres_out' or '-thres_out', where 'thres_out' is the decision threshold set by the parameter 'ISF_params[4]' of the 'compare' primitive. In the 'comp_done' model, this is done with a pair of 'slice' primitives and an 'or_xbit' primitive. Each 'slice' primitive detects whether 'out_r' has reached '+thres_out' or '-thres_out', and the 'or_xbit' primitive asserts the 'done' signal when either condition is true.

module comp_done #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xbit out,                    // decision output
    output xbit done,                   // completion output
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xreal out_r;
xbit trig_d, s1, s2;

compare     #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
            COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out));
and_xbit    DLY (.in({trig, trig}), .out(trig_d));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(out_r), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(out_r), .ctrl(trig_d));
capacitor   #(.C(C)) C1 (.pos(out_r), .neg(`ground));

slice       #(.threshold(thres_out)) SL1 (.in(out_r), .in_ref(`ground), .out(s1));
slice       #(.threshold(thres_out)) SL2 (.in(`ground), .in_ref(out_r), .out(s2));
or_xbit     OR1 (.in({s1, s2}), .out(done));

endmodule

The cellview sandbox.tb_comp_done:schematic is a testbench schematic that observes the outputs 'out' and 'done' of the described 'comp_done' model while varying the net input value from -0.1 to 0.1 over a 1us period. In addition, using a pair of 'trig_posedge' primitives and a 'meas_delay' primitive, the testbench measures the clock-to-done delay of the clocked comparator, that is, the delay between the rising edge of the triggering clock 'trig' and the rising edge of the 'done' output.

The simulated waveforms of using this testbench are shown below. The clocked comparator model initiates a decision process whenever the clock has a rising edge and asserts its 'done' output when the process is complete. The waveform of the signal 'out' confirms that the clocked comparator detects the input polarity correctly, producing 0 while the net input 'in'-'in_ref' is negative and 1 while it is positive. On the other hand, the clock-to-done delay increases exponentially as the net input magnitude approaches to zero. It appears as if it has a maximum value of 500ps, but it is because the clock has a 1ns period and 50% duty-cycle. That is, the comparator cannot reach a decision within the 500ps half period when the net input is too small. In this case, the comparator model does not assert 'done'.

As you mentioned, some clocked comparator designs also employ time-out circuits, which assert the 'done' signal when a certain time period expires even though the decision has not been made yet. In asynchronous SAR ADC designs, this feature helps set the maximum bound on the time required for each comparison cycle and mitigate issues due to metastability.

The following 'comp_done_timeout' model, included as a cellview sandbox.comp_done_timeout:xmodel in the attached package, illustrates how one can add the time-out capability to the 'comp_done' model, by adding a 'transition' primitive ('TR1') and a 'slice' primitive ('SL0'). When the triggering clock 'trig' has a positive edge, the 'transition' primitive produces a ramp signal 'trig_t' that rises from -1.0 to 1.0 with the rise time of twice the time-out period ('timeout'). The 'slice' primitive instance 'SL0' detects when this 'trig_t' crosses 0.0, which would indicate the expiration of time-out period. The 3-input 'or_xbit' primitive ('OR1') asserts the 'done' output when 'SL0' detects such expiration or when 'SL1' or 'SL2' detects that 'out_r' has reached '+thres_out' or '-thres_out', respectively.

module comp_done_timeout #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real timeout = 400e-12,   // Time-out Period
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xbit out,                    // decision output
    output xbit done,                   // completion output
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xreal out_r, trig_t;
xbit trig_d, s0, s1, s2;

compare     #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
            COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out));
and_xbit    DLY (.in({trig, trig}), .out(trig_d));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(out_r), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(out_r), .ctrl(trig_d));
capacitor   #(.C(C)) C1 (.pos(out_r), .neg(`ground));

transition  #(.rise_time(2*timeout), .fall_time(0.0), .value0(-1.0), .value1(1.0))
            TR1 (.in(trig), .out(trig_t));
slice       #(.threshold(0.0)) SL0 (.in(trig_t), .in_ref(`ground), .out(s0));
slice       #(.threshold(thres_out)) SL1 (.in(out_r), .in_ref(`ground), .out(s1));
slice       #(.threshold(thres_out)) SL2 (.in(`ground), .in_ref(out_r), .out(s2));
or_xbit     #(.num_in(3)) OR1 (.in({s0, s1, s2}), .out(done));

endmodule

The simulated waveforms of the 'comp_done_timeout' model using the testbench cellview sandbox.tb_comp_done_timeout are shown below. There are two key differences with the waveforms of the previously-discussed 'comp_done' model. One is that the maximum clock-to-done delay is now 400ps, which is set by the time-out period, instead of the half period of the triggering clock. The other is that even when the net input magnitude is small and clock-to-done delay has the maximum value, the clocked comparator is still producing the valid 'done' signal. This confirms that the time-out functionality is working properly.

The attached package also includes the model of an asynchronous SAR ADC using the 'comp_done_timeout' model for its clocked comparator. The top-level cellview of the SAR ADC is saradc.saradc:schematic and the simulated waveform of its digital output responding to a full-scale sinusoidal input using the testbench saradc.tb_saradc:schematic is shown below.

Attachment: comp_latch_20230829.tar.gz