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Modeling a DAC with finite settling time
How do I model a digital-to-analog converter (DAC) that has a settling behavior like the ones shown below? For instance, a DAC may respond to the input code change with a pure delay (dead time), limits on the slew rate (slew time), or finite settling time due to a first- or second-order linear system characteristics (linear settling time).
Here are a few reference articles written by Bonnie Baker, explaining the terminologies used in the above figures.
- B. Baker, “Designing with a DAC: Setting for the Best,” EDN Asia, January 11, 2018, https://www.ednasia.com/settle-for-the-best/.
- B. Baker, “DAC Basics, Part 5: Settling Down the Impact of the DAC,” Planet Analog, June 16, 2015, https://www.planetanalog.com/dac-basics-part-5-settling-down-the-impact-of-the-dac/.
Yes, here is an easy way to model a digital-to-analog converter (DAC) with the said settling behavior. Combine the 'dac' primitive with the technique described in this Q&A posting:
Here is an example. The attached package contains a cell 'sandbox.dac_settle1', which models an 8-bit DAC with the dead time, maximum slew rate, and first-order settling response.
The 'dac' primitive performs the ideal digital-to-analog conversion. Its output is fed to a 'delay' primitive, which realizes the dead time (=Tdead) with a pure transport delay. Its output then drives a network of 'resistor', 'capacitor', and 'ilimit' primitives, which implements both the settling bandwidth of a first-order linear system (=BW) and the maximum slew rate (=SRmax). Specifically, the bandwidth (BW) is set by the product of the resistance and capacitance values (BW=1/2πRC) and the maximum slew rate is equal to Imax/C, where the current limit 'Imax' is enforced by the 'ilimit' primitive.
The cellview 'sandbox.tb_dac_settle1:schematic' shown below is a simple testbench that simulates the DAC's settling response. The 'pulse_gen' primitive periodically switches all the bits of the DAC input, so we can observe the full-scale step response of the DAC. The assumed parameters are: Tdead=1ns, SRmax=1V/ns, BW=1GHz, and Cout=1pF.
The simulated waveform is shown below. Notice that the settling response of this DAC is similar to the first figure you showed. It exhibits the dead time, slew time, and linear settling time.
The second example with the cell 'sandbox.dac_settle2' illustrates how you can extend this approach to model an 8-bit DAC with a second-order settling response. From what is shown below, you can tell that the only difference is the addition of the 'inductor' primitive, making an RLC network. The second-order linear settling behavior can be specified with two parameters, natural frequency (=wn) and damping factor (zeta), with which we can determine the values of the resistance and inductance for a given capacitance value (=Cout). Again, the 'ilimit' primitive sets the maximum current that can flow into the capacitor, limiting the slew rate of the output voltage (=dVout/dt).
Here is the settling response of this second DAC model, simulated with the testbench cellview 'sandbox.tb_dac_settle2:schematic'. The assumed parameters are: Tdead=1ns, SRmax=5V/ns, wn=2π*2GHz, zeta=0.25, and Cout=1pF. This settling response looks similar to the second figure you showed. It exhibits the dead time, slew time, and linear settling time of a second-order system.
Attachment: dac_settle_20230821.tar.gz
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유한한 정착시간(settling time)을 가진 D/A 컨버터 모델링
아래의 그래프처럼 유한한 정착 반응 (settling response)을 가지는 디지털-아날로그 변환기(digital-to-analog converter; DAC)를 어떻게 모델링할 수 있나요? 예를 들어, DAC의 출력이 입력코드의 변화에 대해 반응할때, 순수 지연시간(dead time), 유한한 슬루율로 인한 시간(slew time), 1차 또는 2차 선형시스템 특성에 의해 결정되는 정착시간 (linear settling time) 등 다양한 요인에 의해 총 정착시간이 결정될 수 있습니다.
아래의 기사 링크들은 위 그래프들에 사용된 여러가지 용어들을 설명해주고 있으니 참고바랍니다.
- B. Baker, “Designing with a DAC: Setting for the Best,” EDN Asia, January 11, 2018, https://www.ednasia.com/settle-for-the-best/.
- B. Baker, “DAC Basics, Part 5: Settling Down the Impact of the DAC,” Planet Analog, June 16, 2015, https://www.planetanalog.com/dac-basics-part-5-settling-down-the-impact-of-the-dac/.
Yes, here is an easy way to model a digital-to-analog converter (DAC) with the said settling behavior. Combine the 'dac' primitive with the technique described in this Q&A posting:
Here is an example. The attached package contains a cell 'sandbox.dac_settle1', which models an 8-bit DAC with the dead time, maximum slew rate, and first-order settling response.
The 'dac' primitive performs the ideal digital-to-analog conversion. Its output is fed to a 'delay' primitive, which realizes the dead time (=Tdead) with a pure transport delay. Its output then drives a network of 'resistor', 'capacitor', and 'ilimit' primitives, which implements both the settling bandwidth of a first-order linear system (=BW) and the maximum slew rate (=SRmax). Specifically, the bandwidth (BW) is set by the product of the resistance and capacitance values (BW=1/2πRC) and the maximum slew rate is equal to Imax/C, where the current limit 'Imax' is enforced by the 'ilimit' primitive.
The cellview 'sandbox.tb_dac_settle1:schematic' shown below is a simple testbench that simulates the DAC's settling response. The 'pulse_gen' primitive periodically switches all the bits of the DAC input, so we can observe the full-scale step response of the DAC. The assumed parameters are: Tdead=1ns, SRmax=1V/ns, BW=1GHz, and Cout=1pF.
The simulated waveform is shown below. Notice that the settling response of this DAC is similar to the first figure you showed. It exhibits the dead time, slew time, and linear settling time.
The second example with the cell 'sandbox.dac_settle2' illustrates how you can extend this approach to model an 8-bit DAC with a second-order settling response. From what is shown below, you can tell that the only difference is the addition of the 'inductor' primitive, making an RLC network. The second-order linear settling behavior can be specified with two parameters, natural frequency (=wn) and damping factor (zeta), with which we can determine the values of the resistance and inductance for a given capacitance value (=Cout). Again, the 'ilimit' primitive sets the maximum current that can flow into the capacitor, limiting the slew rate of the output voltage (=dVout/dt).
Here is the settling response of this second DAC model, simulated with the testbench cellview 'sandbox.tb_dac_settle2:schematic'. The assumed parameters are: Tdead=1ns, SRmax=5V/ns, wn=2π*2GHz, zeta=0.25, and Cout=1pF. This settling response looks similar to the second figure you showed. It exhibits the dead time, slew time, and linear settling time of a second-order system.
Attachment: dac_settle_20230821.tar.gz
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