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Two simple ways to model a track-and-hold circuit
Can you show me how to model a track-and-hold circuit? That is, a circuit that produces the output (out) tracking the analog input (in) while the clock input (clk) is high and holds the last output value while clk is low.
Sure. There are two simple ways of modeling a track-and-hold circuit. One way is to build a circuit-level model (CLM) with the XMODEL's circuit primitives and the other is to build a functional model (FLM) with the XMODEL's function primitives.
First, the circuit-level model of a track-and-hold circuit shown below basically consists of a 'switch' primitive and a 'capacitor' primitive. When the clock input (clk) is high, the switch is on, propagating the input (in) directly to the output (out). On the other hand, when clk is low, the switch is off and the output (out) is held at the voltage stored by the capacitor. A 'buffer' primitive is added at the output as a precaution to prevent any external loads from inadvertently discharging the capacitor. Note that the on-resistance (R) of the switch and capacitance (C) of the capacitor determine the tracking bandwidth (fBW = 1/2πRC).
Second, the functional model of the track-and-hold circuit shown below is made of a 'sample' primitive and a 'select' primitive. When clk is high, the 'select' primitive propagates the input (in) directly to the output (out). On the other hand, when clk is low, the 'select' primitive selects the output of the 'sample' primitive, which produces the value sampled at the last falling edge of clk. Note that a 'nand' primitive is inserted to add a unit timestep delay and avoid possible glitches caused by the unit timestep delay of the 'sample' primitive.
The simulated waveforms of these two track-and-hold circuit models are shown below. Both models work equally well as intended, tracking the inputs while clk is high and holding the outputs while clk is low.
Attachment: track_hold_20230127.tar.gz
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Track-and-hold 회로를 모델링하는 두가지 방법
Track-and-hold 회로를 모델링하는 예제를 보여주실 수 있나요? 즉, 클록 입력(clk)이 high일때는 그 출력(out)이 아날로그 입력(in)을 그대로 따르고(track), clk이 low일때는 마지막 출력값을 유지(hold)하는 회로를 모델링하고 싶습니다.
Sure. There are two simple ways of modeling a track-and-hold circuit. One way is to build a circuit-level model (CLM) with the XMODEL's circuit primitives and the other is to build a functional model (FLM) with the XMODEL's function primitives.
First, the circuit-level model of a track-and-hold circuit shown below basically consists of a 'switch' primitive and a 'capacitor' primitive. When the clock input (clk) is high, the switch is on, propagating the input (in) directly to the output (out). On the other hand, when clk is low, the switch is off and the output (out) is held at the voltage stored by the capacitor. A 'buffer' primitive is added at the output as a precaution to prevent any external loads from inadvertently discharging the capacitor. Note that the on-resistance (R) of the switch and capacitance (C) of the capacitor determine the tracking bandwidth (fBW = 1/2πRC).
Second, the functional model of the track-and-hold circuit shown below is made of a 'sample' primitive and a 'select' primitive. When clk is high, the 'select' primitive propagates the input (in) directly to the output (out). On the other hand, when clk is low, the 'select' primitive selects the output of the 'sample' primitive, which produces the value sampled at the last falling edge of clk. Note that a 'nand' primitive is inserted to add a unit timestep delay and avoid possible glitches caused by the unit timestep delay of the 'sample' primitive.
The simulated waveforms of these two track-and-hold circuit models are shown below. Both models work equally well as intended, tracking the inputs while clk is high and holding the outputs while clk is low.
Attachment: track_hold_20230127.tar.gz
Please login or Register to submit your answer