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Generating XMODEL netlists from testbench schematics described with ‘analogLib’ cells
I have many testbench schematics described with the 'analogLib' cells and I find it tedious to redraw them using the XMODEL primitives. Can GLISTER directly netlist them into the equivalent XMODEL primitives?
Starting with the XMODEL 2022.02 release, GLISTER can directly netlist a selected set of 'analogLib' cells into the equivalent XMODEL primitives.
Currently, GLISTER can directly netlist the following cells of the 'analogLib' library:
- Independent voltage sources:
vsource,vdc,vpulse,vprbs,vbit,vsin,vexp,vpwl - Independent current sources:
isource,idc,ipulse,iprbs,ibit,isin,iexp,ipwl - Voltage-controlled dependent sources:
vccs,vcvs - Passive circuit elements:
res,cap,ind,switch
As an illustrative example, the testbench schematic shown below feeds a sinusoidal signal from a 'vsin' cell of the 'analogLib' library to the input of the XMODEL's 'filter' primitive.
GLISTER can netlist this testbench into the XMODEL/SystemVerilog codes shown below.
Please note that you may still need to make some changes to your existing testbenches. For instance, you may need to add the 'dump' primitive to record the simulated waveforms.
Also, this feature is for netlisting the ideal circuit elements used in the testbench schematics, not for extracting models from the schematics describing real circuits. For that purpose, please use MODELZEN instead.
If your testbench schematic contains an 'analogLib' cell that is not yet supported by GLISTER, please submit your request to the Scientific Analog support team.
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analogLib 셀들로 구성된 테스트벤치 스키매틱에서 XMODEL netlist 생성하기
제게는 analogLib 셀들로 작성한 테스트벤치 스키매틱들이 이미 많이 있는데, 이를 다시 XMODEL primitive 셀들로 작성하려니 엄두가 안나네요. GLISTER가 이 셀들을 동등한 XMODEL primitive들로 변환하면서 netlist를 생성해줄 수 없나요?
Starting with the XMODEL 2022.02 release, GLISTER can directly netlist a selected set of 'analogLib' cells into the equivalent XMODEL primitives.
Currently, GLISTER can directly netlist the following cells of the 'analogLib' library:
- Independent voltage sources:
vsource,vdc,vpulse,vprbs,vbit,vsin,vexp,vpwl - Independent current sources:
isource,idc,ipulse,iprbs,ibit,isin,iexp,ipwl - Voltage-controlled dependent sources:
vccs,vcvs - Passive circuit elements:
res,cap,ind,switch
As an illustrative example, the testbench schematic shown below feeds a sinusoidal signal from a 'vsin' cell of the 'analogLib' library to the input of the XMODEL's 'filter' primitive.
GLISTER can netlist this testbench into the XMODEL/SystemVerilog codes shown below.
Please note that you may still need to make some changes to your existing testbenches. For instance, you may need to add the 'dump' primitive to record the simulated waveforms.
Also, this feature is for netlisting the ideal circuit elements used in the testbench schematics, not for extracting models from the schematics describing real circuits. For that purpose, please use MODELZEN instead.
If your testbench schematic contains an 'analogLib' cell that is not yet supported by GLISTER, please submit your request to the Scientific Analog support team.
Please login or Register to submit your answer