Sure. The schematic below shows such an example modeling a simple integrate-and-fire (I&F) neuron. This neuron model first integrates the sum of the four inputs in1, in2, in3, and in4 weighted by the parameter 'w[1:4]', where each input is assumed to be a binary pulse having a value of 0 or 1. When the integrated value scaled by the parameter 'K' reaches a threshold value defined by the parameter 'thres', the neuron fires an output pulse whose duration is set by the parameter 'pw' and resets the integrated value to 0. The heart of this neuron model is the 'integ_rst' primitive, which performs the integration with resettable output.

The SystemVerilog model netlisted from this schematic shows the full details of this neuron model. For example, the four inputs in1, in2, in3, and in4 are xbit-typed with the logic-1 level of 1.0, which is why the netlisted model has the xbit_to_xreal connectors inserted before the add primitive. On the other hand, the delay of the inv_xbit primitive sets the pulse width of the output spikes and its initial output value must be set to a non-X value in order to avoid the propagation of X's in the reset path during the initialization.

Here is a simple testbench feeding periodic pulses to the four inputs of the I&F neuron model.

And here are the simulated waveforms using the testbench. When any one of the inputs is high, the integral value of the neuron changes at a rate defined by the corresponding weight factor. And when the integral value reaches a threshold (=1.0), the neuron generates a 10ns-long pulse and resets the integral value back to 0.

Attachment: neuron_20220129.tar.gz

Sure. The schematic below shows such an example modeling a simple integrate-and-fire (I&F) neuron. This neuron model first integrates the sum of the four inputs in1, in2, in3, and in4 weighted by the parameter 'w[1:4]', where each input is assumed to be a binary pulse having a value of 0 or 1. When the integrated value scaled by the parameter 'K' reaches a threshold value defined by the parameter 'thres', the neuron fires an output pulse whose duration is set by the parameter 'pw' and resets the integrated value to 0. The heart of this neuron model is the 'integ_rst' primitive, which performs the integration with resettable output.

The SystemVerilog model netlisted from this schematic shows the full details of this neuron model. For example, the four inputs in1, in2, in3, and in4 are xbit-typed with the logic-1 level of 1.0, which is why the netlisted model has the xbit_to_xreal connectors inserted before the add primitive. On the other hand, the delay of the inv_xbit primitive sets the pulse width of the output spikes and its initial output value must be set to a non-X value in order to avoid the propagation of X's in the reset path during the initialization.

Here is a simple testbench feeding periodic pulses to the four inputs of the I&F neuron model.

And here are the simulated waveforms using the testbench. When any one of the inputs is high, the integral value of the neuron changes at a rate defined by the corresponding weight factor. And when the integral value reaches a threshold (=1.0), the neuron generates a 10ns-long pulse and resets the integral value back to 0.

Attachment: neuron_20220129.tar.gz