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Mapping illegal signal names to legal ones when using ‘replay_all’ primitives

SA Support Team Staff 2021-10-01

My testbench schematic uses a 'replay_all' primitive to replay the previously-simulated waveforms stored in FSDB format. Problem is, some of the stored waveforms have illegal names in Verilog, such as "v1:p", causing problems when the 'replay_all' primitive uses the same names for the connected nets. Is there a way to map these illegal names to legal names automatically?

1 Answers

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SA Support Team Staff 2021-10-01

Yes, starting with XMODEL 2021.09 Release, GLISTER supports a user-customizable function called xmodelMapTermNameReplayAll(), which defines the terminal name mapping for 'replay_all' primitives.

Its default definition converts all the colon characters ':' to '__', using the following SKILL codes:

; xmodelMapTermNameReplayAll: user-customizable function for mapping terminal names for replay_all primitive
procedure( xmodelMapTermNameReplayAll( signame )
    signame = pcreReplace( pcreCompile( ":" ) signame "__" 0 )
    signame
)

Users may override this definition in their .cdsinit initialization file for Cadence Virtuoso after the XMODEL/GLISTER context file (xmodel.cxt) is loaded. For instance, to map all the '&' characters to '__' as well, you can modify the definition of the xmodelMapTermNameReplayAll() function as shown below:

; xmodelMapTermNameReplayAll: mapping all ':' and '&' characters to '__'
procedure( xmodelMapTermNameReplayAll( signame )
    signame = pcreReplace( pcreCompile( ":" ) signame "__" 0 )
    signame = pcreReplace( pcreCompile( "&" ) signame "__" 0 )
    signame
)

For information on the Cadence SKILL language using the pcreReplace() and pcreCompile() functions, please refer to the Cadence documentations such as Cadence SKILL Language User Guide and Cadence SKILL Language Reference.

GLISTER

‘replay_all’ primitive를 사용할때 지원하지 않는 문자를 사용한 신호 이름을 정상적인 이름으로 바꾸는 방법

SA Support Team Staff 2021-10-01

테스트벤치 스키메틱에서 'replay_all' primitive를 사용해 이전에 시뮬레이션한 FSDB 형식의 파형들을 재생하고 있습니다. 문제는, 몇몇 파형들의 이름이 Verilog에서 지원하지 않는 문자를 사용하고 있습니다. 예를 들면, "v1:p"처럼 콜론(:)을 포함한 이름입니다. 이때, 'replay_all' primitive의 포트에 연결된 net들도 같은 이름을 가지게 되면서 문제가 발생합니다. 지원하지 않는 문자를 사용한 신호 이름들을 정상적인 이름들로 자동변환하는 방법이 있을까요?

1 Answers

Vote Up 1 Vote Down

Best Answer

SA Support Team Staff 2021-10-01

Yes, starting with XMODEL 2021.09 Release, GLISTER supports a user-customizable function called xmodelMapTermNameReplayAll(), which defines the terminal name mapping for 'replay_all' primitives.

Its default definition converts all the colon characters ':' to '__', using the following SKILL codes:

; xmodelMapTermNameReplayAll: user-customizable function for mapping terminal names for replay_all primitive
procedure( xmodelMapTermNameReplayAll( signame )
    signame = pcreReplace( pcreCompile( ":" ) signame "__" 0 )
    signame
)

; xmodelMapTermNameReplayAll: mapping all ':' and '&' characters to '__'
procedure( xmodelMapTermNameReplayAll( signame )
    signame = pcreReplace( pcreCompile( ":" ) signame "__" 0 )
    signame = pcreReplace( pcreCompile( "&" ) signame "__" 0 )
    signame
)