A quick answer is: yes, XMODEL can compute both voltages and currents of a circuit network, even when the circuit network spans across the module port boundaries. But, no, the 'xreal'-type signal itself does not carry the current value.

When a circuit is described as a group of 'circuit primitives' connected with 'xreal'-type signals, XMODEL computes all the node voltages and branch currents of that circuit responding to the external inputs. This computation is event-driven, leveraging the functional expressions of the 'xreal'-type signals. The 'circuit primitives' composing the circuit may span across different modules, as long as their connections are made with 'xreal'-type signals. Please refer to this link to learn more how XMODEL performs circuit-level simulations in SystemVerilog.

Unlike 'EEnet' in Real-Number Modeling (RNM), the 'xreal'-type signals do not carry the current values, though. In fact, the 'EEnet' way of carrying the current value along with the voltage value with a signal only makes sense for the module ports, as the current flowing through a port can be clearly defined. However, it does not make sense for the internal nets, since the current can only be defined for each branch in the circuit, not for each node.

So in XMODEL, the computed currents are stored within the circuit elements, i.e., 'circuit primitives' that connect between the nodes. For example, the 'resistor' and 'capacitor' primitives have internal variables named 'V', 'I', and 'P', which stores the voltage across the terminals, the current flowing through the terminals, and the instantaneous power dissipated by the element, respectively. You can access them as 'R1.I' and 'C1.I' where 'R1' and 'C1' are the instance names of these primitives. When you need to measure a current flowing through a specific branch, you can insert an 'iprobe' primitive. Similarly, when you want to force a current flow into a branch, you can use an 'isource' primitive. In fact, this way of expressing currents is similar to the way in SPICE. The currents are accessed via expressions such as 'I(V1)', 'I(R1)', and 'I(C1)' where 'V1', 'R1', and 'C1' are the instance names of the voltage source, resistor, and capacitor, respectively.

Here is a simple example that demonstrates the XMODEL's circuit-level simulation capability. It describes a trans-impedance amplifier (TIA) receiving a current input 'Iin' and producing a voltage output 'out'. The TIA is basically a CMOS inverting amplifier enclosed in an RC network and modeled with various circuit primitives of XMODEL: 'isource', 'nmosfet', 'pmosfet', 'resistor' and 'capacitor' primitives. These circuit primitives are connected across the module port boundaries, as the transistors are enclosed in a separate module named 'amp'.

Shown below are the SystemVerilog models netlisted from the above schematic. The circuit primitives are connected via the 'xreal'-type signals and ports.

Now, shown below are the simulated waveforms of the voltages and currents within the circuit. The voltage waveforms are accessed by the signal names while the current waveforms are accessed via the internal variable 'I' of the circuit primitive instances (e.g. 'R1.I' and 'C1.I').

This XMODEL way of modeling circuits as a group of 'circuit primitives' connected with 'xreal'-type signals offers the most natural way of modeling various circuit effects such as loading, nonlinearity, switching, and multiple drivers, in SystemVerilog.

A quick answer is: yes, XMODEL can compute both voltages and currents of a circuit network, even when the circuit network spans across the module port boundaries. But, no, the 'xreal'-type signal itself does not carry the current value.

When a circuit is described as a group of 'circuit primitives' connected with 'xreal'-type signals, XMODEL computes all the node voltages and branch currents of that circuit responding to the external inputs. This computation is event-driven, leveraging the functional expressions of the 'xreal'-type signals. The 'circuit primitives' composing the circuit may span across different modules, as long as their connections are made with 'xreal'-type signals. Please refer to this link to learn more how XMODEL performs circuit-level simulations in SystemVerilog.

Unlike 'EEnet' in Real-Number Modeling (RNM), the 'xreal'-type signals do not carry the current values, though. In fact, the 'EEnet' way of carrying the current value along with the voltage value with a signal only makes sense for the module ports, as the current flowing through a port can be clearly defined. However, it does not make sense for the internal nets, since the current can only be defined for each branch in the circuit, not for each node.

So in XMODEL, the computed currents are stored within the circuit elements, i.e., 'circuit primitives' that connect between the nodes. For example, the 'resistor' and 'capacitor' primitives have internal variables named 'V', 'I', and 'P', which stores the voltage across the terminals, the current flowing through the terminals, and the instantaneous power dissipated by the element, respectively. You can access them as 'R1.I' and 'C1.I' where 'R1' and 'C1' are the instance names of these primitives. When you need to measure a current flowing through a specific branch, you can insert an 'iprobe' primitive. Similarly, when you want to force a current flow into a branch, you can use an 'isource' primitive. In fact, this way of expressing currents is similar to the way in SPICE. The currents are accessed via expressions such as 'I(V1)', 'I(R1)', and 'I(C1)' where 'V1', 'R1', and 'C1' are the instance names of the voltage source, resistor, and capacitor, respectively.

Here is a simple example that demonstrates the XMODEL's circuit-level simulation capability. It describes a trans-impedance amplifier (TIA) receiving a current input 'Iin' and producing a voltage output 'out'. The TIA is basically a CMOS inverting amplifier enclosed in an RC network and modeled with various circuit primitives of XMODEL: 'isource', 'nmosfet', 'pmosfet', 'resistor' and 'capacitor' primitives. These circuit primitives are connected across the module port boundaries, as the transistors are enclosed in a separate module named 'amp'.

Shown below are the SystemVerilog models netlisted from the above schematic. The circuit primitives are connected via the 'xreal'-type signals and ports.

Now, shown below are the simulated waveforms of the voltages and currents within the circuit. The voltage waveforms are accessed by the signal names while the current waveforms are accessed via the internal variable 'I' of the circuit primitive instances (e.g. 'R1.I' and 'C1.I').

This XMODEL way of modeling circuits as a group of 'circuit primitives' connected with 'xreal'-type signals offers the most natural way of modeling various circuit effects such as loading, nonlinearity, switching, and multiple drivers, in SystemVerilog.