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I am generating a model from my circuit using MODELZEN. I want one of its inputs to be a 'wire' type, so I defined the MODELZEN properties of its pin as shown below (using the modelzen_ex.spinv cell from the modelzen_basic tutorial as an example). I defined the XMODEL signal type as 'bit' and defined the logic-1 and logic-0 levels of the signal as 1.2 and 0.0, respectively.
Then MODELZEN generates a model shown below:
The port 'in' is defined as a 'wire' type as expected, and its digital value is converted to an xreal-type signal 'CONN_XREAL0_in' by the bit_to_xreal primitive using the conversion level information 1.2 and 0.0.
For my circuit, the supply voltage 'vdd' is actually not at a fixed voltage of 1.2V. It may change during the operation. So I think that the logic-1 level of the input 'in' should also vary with the 'vdd' level. Is there a way to define the conversion levels as variable with a signal?
Yes, there is. All you have to do is to define the conversion level using the name of the signal! Using your example, you can define the logic-1 level of the port 'in' using the signal name 'vdd' instead of the fixed value of 1.2.
Now, MODELZEN generates a model shown below. The bit_to_xreal primitive is replaced with a bit_to_xreal_var primitive, which converts the wire-type input 'in' into an xreal-type signal 'CONN_XREAL0_in' using the variable logic-1 level equal to the level of 'vdd'.
Please note that you can only use the names of the signals present within the same cell to define the variable conversion levels.
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MODELZEN을 사용해서 회로에서 모델을 생성하고 있습니다. 회로의 입력 중 하나를 wire 타입으로 생성하고 싶어서, 아래에 보이는 것처럼 해당 핀에 MODELZEN 속성을 정의하였습니다. 아래 사진은 modelzen_basic 튜토리얼의 modelzen_ex.spinv 셀을 예로 든 것입니다. 신호의 XMODEL signal type은 'bit'으로 정의하였고, logic-1 레벨과 level-0 레벨은 각각 1.2와 0.0으로 정의하였습니다.
그런 후에, 이 회로로부터 모델을 생성하면 아래의 결과를 얻습니다.
포트 'in'은 예상한대로 'wire' 타입으로 선언되었고, 그 신호가 갖는 디지털 값은 1.2와 0.0을 conversion level 값으로 사용하는 bit_to_xreal primitive에 의해 xreal-타입 내부신호인 CONN_XREAL_0_in으로 변환됩니다.
하지만, 제 회로의 경우에는 전원전압인 'vdd'가 고정된 1.2V의 값을 갖지 않습니다. 즉, 동작 중에 변할 수도 있는 것이죠. 그래서 제 생각에는 이 입력 'in'의 logic-1 레벨의 값이 'vdd' 신호와 연동되어 변해야 한다고 생각합니다. 신호의 conversion level이 신호에 따라 변하게 정의하는 방법이 있나요?
Yes, there is. All you have to do is to define the conversion level using the name of the signal! Using your example, you can define the logic-1 level of the port 'in' using the signal name 'vdd' instead of the fixed value of 1.2.
Now, MODELZEN generates a model shown below. The bit_to_xreal primitive is replaced with a bit_to_xreal_var primitive, which converts the wire-type input 'in' into an xreal-type signal 'CONN_XREAL0_in' using the variable logic-1 level equal to the level of 'vdd'.
Please note that you can only use the names of the signals present within the same cell to define the variable conversion levels.
Please login or Register to submit your answer