In general, it means that you have connected a signal to a port with a different bit size. But if the port under question is an xreal or xbit type port, it is also possible that you may have connected a signal with a different type to the port, since the different type may have a different equivalent bit size. For instance, you may have connected a wire/reg type signal to an xreal type port, or vice versa. Please examine carefully whether the paired signal and port have the same types.

The message you have reported is from NC-Verilog or XCelium. For your information, VCS reports:

Warning-[PCWM-W] Port connection width mismatch

while Questa and ModelSim report:

** Warning: (vsim-3015): [PCDPC] - Port size (137) does not match connection size (1) for port 'a'.

for the same problems.

Depending on the SystemVerilog simulator and the options it is given with, the simulator may report these messages as warnings or errors. Since XMODEL simulations would not properly run with these connection errors and may even terminate with a mysterious error message (e.g. SIGSEGV), we recommend escalating the severity of these messages to errors. Please refer to the documentations of your SystemVerilog simulator on how you can do this.

In general, it means that you have connected a signal to a port with a different bit size. But if the port under question is an xreal or xbit type port, it is also possible that you may have connected a signal with a different type to the port, since the different type may have a different equivalent bit size. For instance, you may have connected a wire/reg type signal to an xreal type port, or vice versa. Please examine carefully whether the paired signal and port have the same types.

The message you have reported is from NC-Verilog or XCelium. For your information, VCS reports:

Warning-[PCWM-W] Port connection width mismatch

while Questa and ModelSim report:

** Warning: (vsim-3015): [PCDPC] - Port size (137) does not match connection size (1) for port 'a'.

for the same problems.

Depending on the SystemVerilog simulator and the options it is given with, the simulator may report these messages as warnings or errors. Since XMODEL simulations would not properly run with these connection errors and may even terminate with a mysterious error message (e.g. SIGSEGV), we recommend escalating the severity of these messages to errors. Please refer to the documentations of your SystemVerilog simulator on how you can do this.