Measuring the phase-domain transfer function of a phase-locked loop (PLL) using the ‘probe_ac’ primitive

Yes, you can. As explained in this Q&A link, the 'probe_ac' primitive provides a convenient way to measure the AC response of a circuit model in a single simulation run. You can extend the use of 'probe_ac' primitive to a broader class of circuit models by combining it with the variable-domain translator (VDT) primitives. The picture below illustrates the basic idea.

For the phase-domain transfer function of a phase-locked loop (PLL), we are interested in the change in the output clock phase in response to the change in the input clock phase. We can measure this phase-domain transfer function by using a pair of 'phase_to_clk' and 'clk_to_phase' primitives in combination with the 'probe_ac' primitive. That is, when the 'probe_ac' primitive produces an AC stimulus which is meant to express the change in the input phase, one can use a 'phase_to_clk' primitive to translate it to an input clock bearing such change in its phase. When the PLL produces an output clock in response to this input clock, one can extract the phase of this output clock using a 'clk_to_phase' primitive, which can then serve as the response signal fed back to the 'probe_ac' primitive. The results measured by the 'probe_ac' primitive would then correspond to the phase-domain transfer function of the PLL.
In fact, this idea can be extended to other circuits that have linear system intents in different variable domains, such as delay-locked loops, frequency-locked loops, duty-cycle corrector loops, etc. For more information, please refer to the following paper: J. Kim, K. D. Jones, M. A. Horowitz, "Variable Domain Transformation for Linear PAC Analysis of Mixed‐Signal Systems," ACM/IEEE International Conference on Computer‐Aided Design (ICCAD), Nov. 2007.
The figure below illustrates the testbench schematic cellview (cp_pll.tb_jtran:schematic) to measure the phase-domain transfer function of a charge-pump PLL model (link). For a PLL that produces a 16GHz output clock from a 2GHz input clock, the 'probe_ac' primitive sweeps its stimulus frequency from 10kHz to 500MHz for a period of 10us. The AC magnitude of the stimulus is kept at a small value of 0.01 and the initial delay is set at 300ns to allow enough time for the PLL to reach its initial lock before the AC frequency sweeping starts. As explained, the 'phase_to_clk' and 'clk_to_phase' primitives set at the nominal frequencies of the input clock (2GHz) and output clock (16GHz), respectively, enable the measurement of the phase-domain transfer function of this PLL.

The following three figures show the setup used for the XMODEL testbench cellview (cp_pll.tb_jtran:tb_ac). The simulation time is set at 11us which sufficiently long for the 'probe_ac' primitive to finish its 10us-long frequency sweeping after the initial delay of 300ns. The explained cp_pll.tb_jtran:schematic cellview is used as the top-level cellview to simulate. And finally, we used the "meas_ac" script instead of the standard "xmodel" to run the simulation and plot waveforms. Please refer to this Q&A link for more information on the "meas_ac" script.



The following figure shows the simulated phase-domain transfer function of the PLL using this testbench. The PLL has a DC gain is at 8 as expected (equal to the frequency multiplication ratio) and has a bandwidth of ~60MHz with a mild peaking. The simulation time of this example was 26 seconds.