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How to model a phase interpolator stage that operates over a wide frequency range
The 'interp_xbit' primitive is great when modeling a phase interpolator stage. But my phase-interpolating CDR has a wide frequency range that spans more than a 2:1 range and I find it almost impossible to satisfy the constraint over all operating frequencies that the delay value of the 'interp_xbit' primitive must be longer than the timing separation of the two inputs being interpolated. Basically, if I set the delay short, the primitive cannot interpolate between two clocks at low frequencies; and if I set the delay long, the primitive cannot propagate the high-frequency clocks. Is there a remedy?
Yes, there is. You can use the 'interp_var_xbit' primitive instead. The 'interp_var_xbit' primitive is similar to the 'interp_xbit' primitive except that its delay is not fixed; it can be controlled by an input signal named 'delay'. By making the delay of the 'interp_var_xbit' primitive scale proportionally with the period of the clocks to be interpolated, you can model a phase interpolator stage that operates over a wide range of frequency. This is in fact consistent with most of the wideband phase interpolators of which bandwidths scale with the operating frequency.
The example below illustrates the use of the 'interp_var_xbit' primitive in modeling a 6-bit digitally-adjustable phase interpolator stage with a wide frequency range. The only difference with the model using the 'interp_xbit' primitive is that the delay of the 'interp_var_xbit' primitive actively scales with the clock period. That is, the combination of the 'clk_to_period' and 'scale' primitives generates a signal 'delay' whose value is equal to a fixed portion of the clock period (e.g. 30% in case of interpolating between the 0° and 90° clocks).
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