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When a schematic cellview contains instances with array names like 'INST<1>', GLISTER and MODELZEN convert them to 'INST__1' to comply with Verilog syntax. Is there a way to customize this format (e.g. to 'INST1')?
To customize the bit-blasting format of instance array names in GLISTER, you can redefine a SKILL function named xmodelFormatInstName(). For instance, if you want a format like 'INST_1_', execute the following lines in the Cadence Virtuoso (e.g. by including them in the .cdsinit file):
; xmodelFormatInstName: define instance name format
procedure( xmodelFormatInstName( name index )
strcat( name "_" index "_" )
)
On the other hand, to customize the bit-blasting format of instance array names in MODELZEN, define a devo_options['format_bitblast'] option value in the MODELZEN technology configuration file. For instance, if you want a format like 'INST_1_', add the following line to the MODELZEN technology configuration file:
devo_options['format_bitblast'] = lambda name, index : "%s_%s_" % (name, index)
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