There are more than one ways to model a clocked comparator latch with the analog outputs. We will show two ways: one is to utilize the regenerated signal 'in_reg' of the 'compare' primitive, and the other is to compose a macromodel of the clocked comparator latch. For each way, we will present two models, one with a single-ended output bearing the net difference value and the other with a pair of differential outputs exhibiting the common-mode transients as well as the differential-mode transients. The attached package contains the models and testbenches that are explained in the following.

The first clocked comparator model, sandbox.comp_latch:xmodel, utilizes the capability of the 'compare' primitive to model a finite-aperture clocked comparator, which can have finite sampling bandwidth and regeneration time. Details on how to use the 'compare' primitive in the finite-aperture mode are given in this Q&A posting. In this mode, the primitive's internal signal named 'in_reg' expresses the transients of the net regenerated signal with which the final decision is made. That is, at the rising edge of the clock input 'trig', the signal 'in_reg' starts tracking the low-pass filtered version of the input signal, and after a trigger delay, the signal is amplified via positive feedback. When 'in_reg' is amplified enough and reaches a certain threshold level, the 'compare' primitive makes a decision, updates its digital output 'out', and holds 'in_reg' at its threshold level. So this signal 'in_reg' exhibits the sampling, regeneration, and decision transients of the net difference output of the clocked comparator latch. But it does not show the resetting behavior when the clock is low. Without an explicit period, the primitive is capable of starting to track the filtered input signal again as soon as the next rising edge of the clock arrives.

The following SystemVerilog code describes the module 'comp_latch', which models a clocked comparator latch with an analog output using the 'compare' primitive. To access the internal signal 'in_reg' of the 'compare' primitive, the model had to be described in the source code form. That is, the expression 'COMP.in_reg' used in the model denotes the 'in_reg' signal of the instance 'COMP' of the 'compare' primitive. The module defines a set of parameters such as 'delay_trig' for the trigger delay, 'gain_smp' and 'tau_smp' for the gain and time constant of the sampling filter, 'tau_reg' for the regeneration time constant, 'tau_rst' for the reset time constant, and 'thres_out' for the decision output threshold. These parameters collectively define the 'ISF_params' parameter of the 'compare' primitive instance, for which the more detailed explanations are given in the above-mentioned Q&A posting.

The additional primitive instances in the model add the resetting behavior to the analog output. That is, while the clock input 'trig' is high, the 'in_reg' signal of the 'compare' primitive instance is passed to the output 'out', which exhibits sampling, regeneration, and decision transients as explained earlier. On the other hand, while 'trig' is low, the output 'out' is discharged towards 0 with a time constant set by the on-resistance of the switch 'SW0' and the capacitance of the capacitor 'C1'. This gives the all the behaviors you are looking for. The 'and_xbit' primitive is to delay the 'trig' input by one simulation timestep, since 'in_reg' of the 'compare' primitive has a one-timestep lag as well.

module comp_latch #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xreal out,                   // signal output
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xbit trig_d, out_d;

compare    #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
           COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out_d));
and_xbit   DELAY (.in({trig, trig}), .out(trig_d));
switch     #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(out), .ctrl(trig_d));
switch     #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(out), .ctrl(trig_d));
capacitor  #(.C(C)) C1 (.pos(out), .neg(`ground));

endmodule

The testbench cellview sandbox.tb_comp_latch:schematic is a simple testbench that observes the output signal of the described 'comp_latch' model while gradually varying the inputs, from the net value of -0.1 to 0.1 over a 1us period.

And the simulated waveforms confirm that the output signal 'out' takes a negative value when the net input value is negative and a positive value when the net input value is positive. And at the vicinity of the input's zero crossing, you can see a gradual change in the output response.

When you take a closer look at this zero crossing, you can find that the 'out' signal of the 'comp_latch' resets towards 0 when the clock input is low and starts getting regenerated when the clock rises to high. The final level 'out' reaches at the end of the clock's high period varies with the net input value ('in'-'in_ref'), but it does not exceed the threshold level (in this example, ±0.5), which is the level where the comparator decision is made.

The following cellview sandbox.comp_latch_diff:schematic extends this 'comp_latch' model to produce a pair of differential outputs. To do so, we need to model the transients of their common-mode level as well, which are done by the additional set of 'switch' and 'capacitor' primitive instances, 'SWC0', 'SWC1', and 'C2'. That is, when the clock input is low, the common-mode level 'vcm' is reset towards a level defined by the parameter 'vcm_rst' (1.0 in this example) with a time constant set by the parameter 'tau_rst'. And when the clock is high, 'vcm' is transitioned towards a level defined by the parameter 'vcm_reg' (0.5 in this example) with a time constant set by the parameter 'tau_reg'. And the final two outputs 'out_p' and 'out_n' are computed as 'vcm+vdm' and 'vcm-vdm', respectively, where 'vdm' is the net output produced by the 'comp_latch' model.

module comp_latch_diff #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real tau_cm = 50e-12,     // Common-mode Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real vcm_reg = 0.5,       // Common-mode Level During Regeneration
    parameter real vcm_rst = 1.0,       // Common-mode Level During Reset
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xreal out_p, out_n,          // signal outputs
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xreal vdm, vcm;
xreal vcm_reg0, vcm_rst0;
xbit trig_d, out_d;

compare     #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
            COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out_d));
and_xbit    DLY (.in({trig, trig}), .out(trig_d));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(vdm), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(vdm), .ctrl(trig_d));
capacitor   #(.C(C)) C1 (.pos(vdm), .neg(`ground));

const_xreal #(.width(2), .value('{vcm_reg, vcm_rst})) CONST (.out({vcm_reg0, vcm_rst0}));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SWC0 (.pos(vcm_rst0), .neg(vcm), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(tau_reg/C)) SWC1 (.pos(vcm_reg0), .neg(vcm), .ctrl(trig_d));
capacitor   #(.C(C)) C2 (.pos(vcm), .neg(`ground));

add         #(.scale('{1.0, 1.0})) ADD_P (.in({vdm, vcm}), .out(out_p));
add         #(.scale('{-1.0, 1.0})) ADD_N (.in({vdm, vcm}), .out(out_n));

endmodule

Here are the simulated waveforms of this 'comp_latch_diff' model using the testbench cellview sandbox.tb_comp_latch_diff:schematic. You can see that the two outputs 'out_p' and 'out_n' of the 'comp_latch_diff' model have the similar transients to what you described. When the clock is low, the two outputs get reset to a high level (1.0 in this example). And when the clock rises, initially the two outputs both fall towards 0.5, but the difference between the two grows over time and eventually one becomes high at 1.0 and the other becomes low at 0.0.

One caveat with this clocked comparator latch model utilizing the 'compare' primitive is that it does not model the effect due to "incomplete reset". In other words, when the reset period is not long enough compared to the reset time constant ('tau_rst'), the result from one cycle may get carried over to the next cycles. For example, the incomplete reset can cause hysteresis in the clocked comparator. That is, the effective threshold of the comparator can change depending on the previous state of the circuit.

Another way to model the clocked comparator latch can address this shortcoming. The model schematic cellview sandbox.comp_latch2:schematic shown below is basically a macromodel of a clocked comparator latch circuit, performing reset, sampling, regeneration, and decision operations using equivalent circuit models.

First, the 'add' primitive computes the net difference between the two inputs 'in' and 'in_ref'. When the clock input 'trig' is high, the resulting signal propagates through a 'scale', 'switch', and 'capacitor' primitives, which collectively perform the role of a sampling filter with a gain of 'gain_smp' and time constant of 'tau_smp'. On the other hand, a 'delay_xbit' and 'and_xbit' primitives produce a signal 'trig_r' which delays the positive edge of the 'trig' input by the trigger delay 'delay_trig'. This 'trig_r' signal is used to enable another 'switch' primitive that has a negative on-resistance whose value is set based on the regeneration time constant 'tau_reg'. The negative on-resistance value implies that the RC filter formed with this switch and the output capacitance will amplify the initial voltage stored on the capacitor exponentially over time instead of decaying it. The 'vlimit' primitive keeps this voltage within the decision threshold levels of '±thres_out', that is, holding the voltage once a decision is made. Finally, when 'trig' falls low, both the sampling switch and regeneration switch become off and a third switch is turned on to discharge the capacitor voltage towards zero with a time constant of 'tau_rst'. Note that this capacitor voltage has all the transients we are looking for: sampling, regeneration, decision, and reset. So it becomes the analog output 'out' of this clocked comparator model.

The simulated waveforms of this 'comp_latch2' model using the testbench cellview sandbox.tb_comp_latch2:schematic are shown below. The waveform of its output 'out' looks quite similar to that of 'out' of the 'comp_latch' model discussed earlier. One difference is that this 'comp_latch2' model has a capability of carrying the internal state of the comparator from one clock cycle to another. For example, when the capacitor voltage does not fully return to 0 during the reset period, the residual voltage can affect the operation of the next cycle, causing hysteresis. Using the provided model and testbench, you can observe the effects due to incomplete reset by increasing the value of the parameter 'tau_rst' (e.g. 200ps).

Now, the cellview sandbox.comp_latch_diff2:schematic shown below is a model that extends 'comp_latch2' to produce a pair of differential outputs. Again, a set of switches and capacitor produces the transients of the common-mode level 'vcm' and the final outputs 'out_p' and 'out_n' are computed as 'vcm+vdm' and 'vcm-vdm', respectively, using 'add' primitives.

Finally, the simulated waveforms of this 'comp_latch_diff2' model using the testbench cellview sandbox.tb_comp_latch_diff2:schematic are shown below. The waveforms of the two outputs 'out_p' and 'out_n' are quite similar to those of 'comp_latch_diff', exhibiting the reset transients towards 1.0 when the clock is low, and exhibiting the sampling, regeneration, and decision transients with the common-mode level approaching to 0.5 when the clock is high.

Attachment: comp_latch_20230829.tar.gz

There are more than one ways to model a clocked comparator latch with the analog outputs. We will show two ways: one is to utilize the regenerated signal 'in_reg' of the 'compare' primitive, and the other is to compose a macromodel of the clocked comparator latch. For each way, we will present two models, one with a single-ended output bearing the net difference value and the other with a pair of differential outputs exhibiting the common-mode transients as well as the differential-mode transients. The attached package contains the models and testbenches that are explained in the following.

The first clocked comparator model, sandbox.comp_latch:xmodel, utilizes the capability of the 'compare' primitive to model a finite-aperture clocked comparator, which can have finite sampling bandwidth and regeneration time. Details on how to use the 'compare' primitive in the finite-aperture mode are given in this Q&A posting. In this mode, the primitive's internal signal named 'in_reg' expresses the transients of the net regenerated signal with which the final decision is made. That is, at the rising edge of the clock input 'trig', the signal 'in_reg' starts tracking the low-pass filtered version of the input signal, and after a trigger delay, the signal is amplified via positive feedback. When 'in_reg' is amplified enough and reaches a certain threshold level, the 'compare' primitive makes a decision, updates its digital output 'out', and holds 'in_reg' at its threshold level. So this signal 'in_reg' exhibits the sampling, regeneration, and decision transients of the net difference output of the clocked comparator latch. But it does not show the resetting behavior when the clock is low. Without an explicit period, the primitive is capable of starting to track the filtered input signal again as soon as the next rising edge of the clock arrives.

The following SystemVerilog code describes the module 'comp_latch', which models a clocked comparator latch with an analog output using the 'compare' primitive. To access the internal signal 'in_reg' of the 'compare' primitive, the model had to be described in the source code form. That is, the expression 'COMP.in_reg' used in the model denotes the 'in_reg' signal of the instance 'COMP' of the 'compare' primitive. The module defines a set of parameters such as 'delay_trig' for the trigger delay, 'gain_smp' and 'tau_smp' for the gain and time constant of the sampling filter, 'tau_reg' for the regeneration time constant, 'tau_rst' for the reset time constant, and 'thres_out' for the decision output threshold. These parameters collectively define the 'ISF_params' parameter of the 'compare' primitive instance, for which the more detailed explanations are given in the above-mentioned Q&A posting.

The additional primitive instances in the model add the resetting behavior to the analog output. That is, while the clock input 'trig' is high, the 'in_reg' signal of the 'compare' primitive instance is passed to the output 'out', which exhibits sampling, regeneration, and decision transients as explained earlier. On the other hand, while 'trig' is low, the output 'out' is discharged towards 0 with a time constant set by the on-resistance of the switch 'SW0' and the capacitance of the capacitor 'C1'. This gives the all the behaviors you are looking for. The 'and_xbit' primitive is to delay the 'trig' input by one simulation timestep, since 'in_reg' of the 'compare' primitive has a one-timestep lag as well.

module comp_latch #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xreal out,                   // signal output
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xbit trig_d, out_d;

compare    #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
           COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out_d));
and_xbit   DELAY (.in({trig, trig}), .out(trig_d));
switch     #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(out), .ctrl(trig_d));
switch     #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(out), .ctrl(trig_d));
capacitor  #(.C(C)) C1 (.pos(out), .neg(`ground));

endmodule

The testbench cellview sandbox.tb_comp_latch:schematic is a simple testbench that observes the output signal of the described 'comp_latch' model while gradually varying the inputs, from the net value of -0.1 to 0.1 over a 1us period.

And the simulated waveforms confirm that the output signal 'out' takes a negative value when the net input value is negative and a positive value when the net input value is positive. And at the vicinity of the input's zero crossing, you can see a gradual change in the output response.

When you take a closer look at this zero crossing, you can find that the 'out' signal of the 'comp_latch' resets towards 0 when the clock input is low and starts getting regenerated when the clock rises to high. The final level 'out' reaches at the end of the clock's high period varies with the net input value ('in'-'in_ref'), but it does not exceed the threshold level (in this example, ±0.5), which is the level where the comparator decision is made.

The following cellview sandbox.comp_latch_diff:schematic extends this 'comp_latch' model to produce a pair of differential outputs. To do so, we need to model the transients of their common-mode level as well, which are done by the additional set of 'switch' and 'capacitor' primitive instances, 'SWC0', 'SWC1', and 'C2'. That is, when the clock input is low, the common-mode level 'vcm' is reset towards a level defined by the parameter 'vcm_rst' (1.0 in this example) with a time constant set by the parameter 'tau_rst'. And when the clock is high, 'vcm' is transitioned towards a level defined by the parameter 'vcm_reg' (0.5 in this example) with a time constant set by the parameter 'tau_reg'. And the final two outputs 'out_p' and 'out_n' are computed as 'vcm+vdm' and 'vcm-vdm', respectively, where 'vdm' is the net output produced by the 'comp_latch' model.

module comp_latch_diff #(
    parameter real delay_trig = 0.0,    // Trigger Delay
    parameter real gain_smp = 1.0,      // Sampling Gain
    parameter real tau_smp = 100e-12,   // Sampling Time Constant
    parameter real tau_reg = 100e-12,   // Regeneration Time Constant
    parameter real tau_rst = 50e-12,    // Reset Time Constant
    parameter real tau_cm = 50e-12,     // Common-mode Time Constant
    parameter real thres_out = 0.5,     // Output Threshold
    parameter real vcm_reg = 0.5,       // Common-mode Level During Regeneration
    parameter real vcm_rst = 1.0,       // Common-mode Level During Reset
    parameter real noise_in = 0.0,      // RMS Input-Referred Noise
    parameter real C = 1e-12            // Internal Capacitance
)(
    output xreal out_p, out_n,          // signal outputs
    input xreal in,                     // signal input
    input xreal in_ref,                 // reference input
    input xbit trig                     // trigger input
);

xreal vdm, vcm;
xreal vcm_reg0, vcm_rst0;
xbit trig_d, out_d;

compare     #(.noise_in(noise_in), .ISF_params('{delay_trig,gain_smp,tau_smp,tau_reg,thres_out}))
            COMP (.in(in), .in_ref(in_ref), .trig(trig), .out(out_d));
and_xbit    DLY (.in({trig, trig}), .out(trig_d));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SW0 (.pos(`ground), .neg(vdm), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(0.0)) SW1 (.pos(COMP.in_reg), .neg(vdm), .ctrl(trig_d));
capacitor   #(.C(C)) C1 (.pos(vdm), .neg(`ground));

const_xreal #(.width(2), .value('{vcm_reg, vcm_rst})) CONST (.out({vcm_reg0, vcm_rst0}));
switch      #(.R0(tau_rst/C), .R1(`INFINITY)) SWC0 (.pos(vcm_rst0), .neg(vcm), .ctrl(trig_d));
switch      #(.R0(`INFINITY), .R1(tau_reg/C)) SWC1 (.pos(vcm_reg0), .neg(vcm), .ctrl(trig_d));
capacitor   #(.C(C)) C2 (.pos(vcm), .neg(`ground));

add         #(.scale('{1.0, 1.0})) ADD_P (.in({vdm, vcm}), .out(out_p));
add         #(.scale('{-1.0, 1.0})) ADD_N (.in({vdm, vcm}), .out(out_n));

endmodule

Here are the simulated waveforms of this 'comp_latch_diff' model using the testbench cellview sandbox.tb_comp_latch_diff:schematic. You can see that the two outputs 'out_p' and 'out_n' of the 'comp_latch_diff' model have the similar transients to what you described. When the clock is low, the two outputs get reset to a high level (1.0 in this example). And when the clock rises, initially the two outputs both fall towards 0.5, but the difference between the two grows over time and eventually one becomes high at 1.0 and the other becomes low at 0.0.

One caveat with this clocked comparator latch model utilizing the 'compare' primitive is that it does not model the effect due to "incomplete reset". In other words, when the reset period is not long enough compared to the reset time constant ('tau_rst'), the result from one cycle may get carried over to the next cycles. For example, the incomplete reset can cause hysteresis in the clocked comparator. That is, the effective threshold of the comparator can change depending on the previous state of the circuit.

Another way to model the clocked comparator latch can address this shortcoming. The model schematic cellview sandbox.comp_latch2:schematic shown below is basically a macromodel of a clocked comparator latch circuit, performing reset, sampling, regeneration, and decision operations using equivalent circuit models.

First, the 'add' primitive computes the net difference between the two inputs 'in' and 'in_ref'. When the clock input 'trig' is high, the resulting signal propagates through a 'scale', 'switch', and 'capacitor' primitives, which collectively perform the role of a sampling filter with a gain of 'gain_smp' and time constant of 'tau_smp'. On the other hand, a 'delay_xbit' and 'and_xbit' primitives produce a signal 'trig_r' which delays the positive edge of the 'trig' input by the trigger delay 'delay_trig'. This 'trig_r' signal is used to enable another 'switch' primitive that has a negative on-resistance whose value is set based on the regeneration time constant 'tau_reg'. The negative on-resistance value implies that the RC filter formed with this switch and the output capacitance will amplify the initial voltage stored on the capacitor exponentially over time instead of decaying it. The 'vlimit' primitive keeps this voltage within the decision threshold levels of '±thres_out', that is, holding the voltage once a decision is made. Finally, when 'trig' falls low, both the sampling switch and regeneration switch become off and a third switch is turned on to discharge the capacitor voltage towards zero with a time constant of 'tau_rst'. Note that this capacitor voltage has all the transients we are looking for: sampling, regeneration, decision, and reset. So it becomes the analog output 'out' of this clocked comparator model.

The simulated waveforms of this 'comp_latch2' model using the testbench cellview sandbox.tb_comp_latch2:schematic are shown below. The waveform of its output 'out' looks quite similar to that of 'out' of the 'comp_latch' model discussed earlier. One difference is that this 'comp_latch2' model has a capability of carrying the internal state of the comparator from one clock cycle to another. For example, when the capacitor voltage does not fully return to 0 during the reset period, the residual voltage can affect the operation of the next cycle, causing hysteresis. Using the provided model and testbench, you can observe the effects due to incomplete reset by increasing the value of the parameter 'tau_rst' (e.g. 200ps).

Now, the cellview sandbox.comp_latch_diff2:schematic shown below is a model that extends 'comp_latch2' to produce a pair of differential outputs. Again, a set of switches and capacitor produces the transients of the common-mode level 'vcm' and the final outputs 'out_p' and 'out_n' are computed as 'vcm+vdm' and 'vcm-vdm', respectively, using 'add' primitives.

Finally, the simulated waveforms of this 'comp_latch_diff2' model using the testbench cellview sandbox.tb_comp_latch_diff2:schematic are shown below. The waveforms of the two outputs 'out_p' and 'out_n' are quite similar to those of 'comp_latch_diff', exhibiting the reset transients towards 1.0 when the clock is low, and exhibiting the sampling, regeneration, and decision transients with the common-mode level approaching to 0.5 when the clock is high.

Attachment: comp_latch_20230829.tar.gz