Auto-generating models with all the top-level ports as real types

SA Support Team Staff 2023-07-27

I’m planning to use the SystemVerilog models generated by MODELZEN in the Cadence AMS environment. Without the AMS connect modules available for xreal-type signals, I’d like the SystemVerilog models to have all the top-level ports defined as real types.

I know setting the MODELZEN properties and defining the XMODEL signal types of the ports to 'real' can achieve what I want. But when the number of ports is large, the task becomes very tedious. Moreover, I don’t want to set these MODELZEN properties to my schematic cells permanently — I only want to set them when the cell serves as the top-level module. However, I don’t want to repeatedly set and unset the MODELZEN properties every time I generate a model using a different cell.

Is there a more convenient way to generate a model with its top-level ports as real types?

1 Answers

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SA Support Team Staff 2023-07-27

Yes, there is. XMODEL 2023.06 Release added the '--real' option to MODELZEN. With this '--real' option, you can define a list of modules whose I/O ports shall be 'real' types unless there are overriding MODELZEN properties.

For example, the following command would extract the SystemVerilog model from the input netlist 'input.sp' with all the input and output ports of the module named 'MYCELL' defined as real types.

modelzen input.sp --real MYCELL

If you want to specify the top-level module without its explicit name, you can use the '__TOP__' alias:

modelzen input.sp --real __TOP__

Then, MODELZEN will generate the model from the input netlist with all of its top-level ports as real types.

To achieve the same using the GUI interface of MODELZEN, you can add '__TOP__' to the field named "Modules with real-type Ports" located in the "Signal" tab as shown below.

And in case you want this to be a default behavior of MODELZEN, you can add the following line in its technology configuration file:

devo_options['modules_real'] = ['__TOP__']

MODELZEN

모든 최상위 포트를 real 타입으로 갖는 모델 자동생성하기

SA Support Team Staff 2023-07-27

MODELZEN으로 생성한 SystemVerilog 모델을 Cadence의 AMS 환경에서 사용하려고 합니다. xreal 타입 신호를 지원하는 AMS connect module은 아직 없기에, 이 SystemVerilog 모델의 최상위 포트들은 real 타입 신호로 생성하고 싶습니다.

MODELZEN property들을 설정하여 해당 포트들의 XMODEL signal type을 모두 'real'로 설정하면, 제가 원하는 형태의 모델을 생성할 수 있음을 압니다. 하지만, 포트의 수가 많아지면 이 방법은 너무 귀찮은 작업을 요구합니다. 게다가, 저의 스키매틱 셀에 포트 타입을 real로 설정하는 MODELZEN property들을 영구히 남겨놓고 싶지도 않습니다. 그 셀을 최상위 셀로 삼아서 모델을 생성할 때만 잠시 MODELZEN property들을 설정하고 싶은데, 그럴려면 모델을 생성할 때마다 MODELZEN property들을 설정했다 지웠다를 반복해야 하는 것 같습니다.

모델의 최상위 포트를 모두 real 타입으로 생성하는 보다 편리한 방법이 없을까요?

1 Answers

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SA Support Team Staff 2023-07-27

For example, the following command would extract the SystemVerilog model from the input netlist 'input.sp' with all the input and output ports of the module named 'MYCELL' defined as real types.

modelzen input.sp --real MYCELL

If you want to specify the top-level module without its explicit name, you can use the '__TOP__' alias:

modelzen input.sp --real __TOP__

Then, MODELZEN will generate the model from the input netlist with all of its top-level ports as real types.

To achieve the same using the GUI interface of MODELZEN, you can add '__TOP__' to the field named "Modules with real-type Ports" located in the "Signal" tab as shown below.

And in case you want this to be a default behavior of MODELZEN, you can add the following line in its technology configuration file:

devo_options['modules_real'] = ['__TOP__']